Commit Graph

9940 Commits

Author SHA1 Message Date
Dolu1990 59fc1caac4
Merge pull request #2099 from VOGL-electronic/vexiiriscv_sbi
vexiiriscv: add options and conditions
2024-10-25 14:26:02 +02:00
Fin Maaß 773fb34079
vexiiriscv: have opensbi behind a option
this way opensbi things are only activated,
when a linux variant is used.

Signed-off-by: Fin Maaß <f.maass@vogl-electronic.com>
2024-10-25 13:40:20 +02:00
Andelf 8c7e510473 Fixes #2103: calculate memory depth for WS2812
See-also: https://github.com/m-labs/migen/pull/295
2024-10-25 11:48:57 +08:00
Dolu1990 24db36ced5 Merge remote-tracking branch 'origin/master' into wuff 2024-10-24 16:02:52 +02:00
Dolu1990 375940ad7d soc/core/vexiiriscv: add macsg support (dma based ethernet) 2024-10-24 16:00:51 +02:00
Fin Maaß d7bf75a75c
bios: litespi: add newline to debug output
add newline to debug output

Signed-off-by: Fin Maaß <f.maass@vogl-electronic.com>
2024-10-24 15:12:12 +02:00
Fin Maaß 63fa4fda85
bios: litespi: clear rx queue after write
clear rx queue at the end of spiflash_master_write().

Signed-off-by: Fin Maaß <f.maass@vogl-electronic.com>
2024-10-24 15:10:37 +02:00
Fin Maaß 54973eb9cb
build: efinix: use constant output option
use constant output option, when the output is a `Constant`

Signed-off-by: Fin Maaß <f.maass@vogl-electronic.com>
2024-10-23 14:12:30 +02:00
Fin Maaß 2d96e99494
build: io: SDRTristate: move check
check wraped signals instead of before.

Signed-off-by: Fin Maaß <f.maass@vogl-electronic.com>
2024-10-23 11:18:57 +02:00
Fin Maaß 70f4a349e5
efinix: ifacewriter: fix in output
fix in OUTPUT

Signed-off-by: Fin Maaß <f.maass@vogl-electronic.com>
2024-10-23 11:10:16 +02:00
Fin Maaß d6eec8e76d
efinix: ifacewriter: gpio: share common code
share common code for INPUT, INOUT and OUTPUT.

Signed-off-by: Fin Maaß <f.maass@vogl-electronic.com>
2024-10-23 11:08:58 +02:00
enjoy-digital c1225736a8
Merge pull request #2098 from enjoy-digital/urv
Add initial uRV CPU support.
2024-10-17 19:45:44 +02:00
Florent Kermarrec 5f463dba87 CHANGES.md: Update. 2024-10-17 17:45:50 +02:00
Florent Kermarrec aab8912f5a soc/cores/cpu/urv: Move ROM init to builder and allow switching between classical ROM or ROM integrated in CPU. 2024-10-17 17:44:40 +02:00
Florent Kermarrec 9449d25911 soc/cores/cpu/urv: Able to boot LiteX BIOS with im bus connected to synchronous memory.
- Replace im bus wishbone adaptation with synchronous memory (for now and initial tests).
- Correctly handle dm bus wishbone adaptation (Added FIFO).
2024-10-17 16:54:20 +02:00
Florent Kermarrec edb56e73aa soc/cores/cpu: Add initial uRV CPU support (not yet working). 2024-10-16 22:24:07 +02:00
Gwenhael Goavec-Merou 06f9f9780d litex/soc/cores/jtag.py: lattice target: INIT -> init (otherwise fails with diamond) 2024-10-16 13:47:42 +02:00
Gwenhael Goavec-Merou ea81314866 build/lattice/diamond.py,platform.py: allows adding custom strategy 2024-10-16 13:46:43 +02:00
Gwenhael Goavec-Merou 331e1938c9 build/lattice/diamond.py,platform.py: allows adding lattice's IPs 2024-10-16 13:45:57 +02:00
Gwenhael Goavec-Merou c4943c1c5d build/lattice/diamond.py: allows adding addition ldf commands in tcl 2024-10-16 13:44:20 +02:00
Florent Kermarrec c82fddf635 CHANGES.md: Update. 2024-10-15 12:54:37 +02:00
Dolu1990 d5e4f9e975 soc/core/vexiiriscv : bring back xilinx support 2024-10-15 09:36:32 +02:00
Gwenhael Goavec-Merou 7f04cafe08 soc/cores/cpu/zynqmp/core.py: add_ethernet: added gt_location required by SGMII 2024-10-10 17:28:29 +02:00
Gwenhael Goavec-Merou 2935b7afb1 soc/cores/cpu/zynqmp/core.py: added missing pps signals 2024-10-10 17:26:35 +02:00
Florent Kermarrec dc3364a3c7 CHANGES.md: Update. 2024-10-09 16:42:05 +02:00
enjoy-digital 01c7a78f67
Merge pull request #2095 from trabucayre/zynqmp_ethernet_sgmii
soc/cores/cpu/zynqmp/core.py: added support for SGMII via PL with optional PTP support
2024-10-09 16:38:33 +02:00
Gwenhael Goavec-Merou ddb8d16381 soc/cores/cpu/zynqmp/core.py: added support for SGMII via PL with option PTP support 2024-10-09 16:14:31 +02:00
Gwenhael Goavec-Merou 34b98ab578
Merge pull request #2093 from mgaggero/feature-alpine-linux
Fixes #2092: provides support for riscv gcc installation on Alpine Linux.
2024-10-09 06:32:05 +02:00
Massimo Gaggero e148650279 Fixes #2092: provides support for riscv gcc installation on Alpine
Linux.
2024-10-08 20:46:38 +02:00
Gwenhael Goavec-Merou bc3e90c93a
Merge pull request #2090 from VOGL-electronic/efinix_iobank
build: efinix: use ifacewriter to set bank voltage
2024-10-08 09:54:20 +02:00
Fin Maaß d26994916d
build: efinix: use ifacewriter to set bank voltage
use efinix python api to set bank voltage,
instead of editing the peri.xml file.

Signed-off-by: Fin Maaß <f.maass@vogl-electronic.com>
2024-10-08 09:05:04 +02:00
enjoy-digital 9ad5d21231
Merge pull request #2089 from VOGL-electronic/efinix_tristate_fix
build: efinix: Tristate fix
2024-10-07 11:06:26 +02:00
Fin Maaß 4fcae9f3c7
build: efinix: Tristate fix
fix efinix Tristate by adding size to add_iface_io().

Signed-off-by: Fin Maaß <f.maass@vogl-electronic.com>
2024-10-07 10:15:38 +02:00
Florent Kermarrec 64cf925b39 soc/integration/soc: Cleanup imports and directly use math.log2/ceil since math is already imported. 2024-10-02 17:10:08 +02:00
Florent Kermarrec 5e897752b7 soc/intergration/soc/add_pcie: Add new status_width parameter. 2024-10-02 17:10:05 +02:00
enjoy-digital 644ef7e4e5
Merge pull request #2086 from VOGL-electronic/build_io_clocksignal
build: io: don't use mutable object as default value
2024-10-01 11:49:03 +02:00
Fin Maaß 280b6b4ee4
build: io: don't use mutable object as default value
don't use mutable object (here: ClockSignal()) as default value,
beacuse they will be the same object.
Leeds to problems, when for example two `SDRInput`
are used in two different Modules and one of them is
used with a `ClockDomainsRenamer()`, then both are changed.

Signed-off-by: Fin Maaß <f.maass@vogl-electronic.com>
2024-09-30 15:18:11 +02:00
Florent Kermarrec 87ee6ec3a0 CHANGES.md: Prepare for post 2024.08 changes. 2024-09-27 09:58:09 +02:00
Florent Kermarrec f72368abaa CHANGES.md: Do 2024.08 release. 2024-09-27 09:45:11 +02:00
Florent Kermarrec 58e916d86e setup.py: 2024.08 release. 2024-09-27 09:37:11 +02:00
Florent Kermarrec 50bb6bb1ff CHANGES.md: Update. 2024-09-27 09:33:22 +02:00
Florent Kermarrec 2130ff2fb3 build/efinix/efinity: Cosmetic cleanup on toolchain arguments. 2024-09-26 18:06:36 +02:00
Florent Kermarrec 1568b25ff7 build/efinix/common: Cosmetic cleanups. 2024-09-26 18:03:36 +02:00
Florent Kermarrec 431feb0ac2 build/efinix/common: Enable back SDRInput since support fixed with recent changes. 2024-09-26 18:01:02 +02:00
Florent Kermarrec 9760493c32 build/efinix/common: Switch to LiteXModule. 2024-09-26 17:46:07 +02:00
enjoy-digital 95e5e7302e
Merge pull request #2083 from VOGL-electronic/efinix_common_improve
build: efinix: EfinixTristateImpl: use GPIO Bus
2024-09-26 17:41:07 +02:00
enjoy-digital c67dfa82cc
Merge pull request #2079 from VOGL-electronic/efinix_iface_fixups
build: efinix: ifacewriter: some fixes
2024-09-26 17:31:53 +02:00
Fin Maaß a825c61385 build: efinix: EfinixTristateImpl: use GPIO Bus
use the gpio bus for Efinix Tristate implemenation.

Signed-off-by: Fin Maaß <f.maass@vogl-electronic.com>
2024-09-26 16:03:56 +02:00
Fin Maaß e9a4b178ce build: efinix: platform.py: add `get_pins_location` and `get_pins_name`
add `get_pins_location` and  `get_pins_name`.

Signed-off-by: Fin Maaß <f.maass@vogl-electronic.com>
2024-09-26 16:03:56 +02:00
Fin Maaß f8dc03810d build: efinix: use LiteXContext to get platform
use LiteXContext to get platform.

Signed-off-by: Fin Maaß <f.maass@vogl-electronic.com>
2024-09-26 16:03:41 +02:00