Sebastien Bourdeauducq
|
3b19dfc412
|
Support for platform info
|
2013-03-26 19:17:35 +01:00 |
|
Sebastien Bourdeauducq
|
74cc4d22cd
|
generic_platform: remove obj in request + add lookup_request
|
2013-03-26 17:56:53 +01:00 |
|
Sebastien Bourdeauducq
|
003f1950cd
|
xilinx_ise: fix clock domain names
|
2013-03-23 19:37:16 +01:00 |
|
Sebastien Bourdeauducq
|
797411c1a9
|
generic_platform: do not create clock domains during Verilog conversion
|
2013-03-18 18:44:58 +01:00 |
|
Sebastien Bourdeauducq
|
4bf3190244
|
MultiReg: remove idomain
|
2013-03-15 19:54:25 +01:00 |
|
Sebastien Bourdeauducq
|
6feb6e60b0
|
New clock_domain API
|
2013-03-15 18:46:11 +01:00 |
|
Sebastien Bourdeauducq
|
001beadb97
|
altera_quartus, de0nano: add copyright notices
|
2013-03-15 12:37:25 +01:00 |
|
Sebastien Bourdeauducq
|
f9e07b92a4
|
Added platform file for DE0 Nano (by Florent Kermarrec)
|
2013-03-15 11:41:38 +01:00 |
|
Sebastien Bourdeauducq
|
86d6f1d011
|
Added support for Altera Quartus (by Florent Kermarrec)
|
2013-03-15 11:32:12 +01:00 |
|
Sebastien Bourdeauducq
|
71c8172836
|
xilinx_ise/CRG_SE: reset inversion support
|
2013-03-15 11:31:36 +01:00 |
|
Sebastien Bourdeauducq
|
37d8029848
|
CRG: support reset inversion
|
2013-03-15 10:49:18 +01:00 |
|
Sebastien Bourdeauducq
|
24910173b7
|
CRG: use new Module API
|
2013-03-15 10:48:43 +01:00 |
|
Sebastien Bourdeauducq
|
c06a821452
|
generic_platform: implicit get_fragment
|
2013-03-12 16:14:13 +01:00 |
|
Sebastien Bourdeauducq
|
4d4d6c1f88
|
platforms/m1: add video mixer extension board
|
2013-03-05 23:03:01 +01:00 |
|
Sebastien Bourdeauducq
|
6a412f796e
|
xilinx_ise: add lock cycle to bitgen
|
2013-03-01 11:29:40 +01:00 |
|
Sebastien Bourdeauducq
|
2b902fdcbd
|
xilinx_ise: import Instance
|
2013-02-24 15:36:56 +01:00 |
|
Sebastien Bourdeauducq
|
d60ab1d215
|
Use new 'specials' API
|
2013-02-24 12:21:01 +01:00 |
|
Sebastien Bourdeauducq
|
56ae0f0714
|
xilinx_ise: disable SRL extraction on synchronizers
|
2013-02-23 19:43:12 +01:00 |
|
Sebastien Bourdeauducq
|
ef833422c7
|
generic_platform/get_verilog: pass additional args to verilog.convert
|
2013-02-23 19:42:29 +01:00 |
|
Sebastien Bourdeauducq
|
0321513726
|
corelogic -> genlib
|
2013-02-23 19:37:27 +01:00 |
|
Sebastien Bourdeauducq
|
44ae20d3c4
|
generic_platform: prefix subsignals
|
2013-02-20 18:27:04 +01:00 |
|
Sebastien Bourdeauducq
|
38c3566717
|
generic_platform: add name
|
2013-02-14 20:02:35 +01:00 |
|
Sebastien Bourdeauducq
|
ed4d65f2be
|
generic_platform: fix IO signal set when using existing record objects
|
2013-02-13 23:29:33 +01:00 |
|
Sebastien Bourdeauducq
|
feec035cc8
|
generic_platform: get absolute path for added sources
|
2013-02-12 19:16:00 +01:00 |
|
Sebastien Bourdeauducq
|
709845e618
|
generic_platform: fix request
|
2013-02-11 17:54:01 +01:00 |
|
Sebastien Bourdeauducq
|
ce6701c6e4
|
platforms/m1: norflash_reset -> norflash_rst_n
|
2013-02-11 17:46:27 +01:00 |
|
Sebastien Bourdeauducq
|
4b78d90aad
|
platforms/m1: add serial pins
|
2013-02-11 17:46:03 +01:00 |
|
Sebastien Bourdeauducq
|
f13ad035e1
|
Support for command line arguments
|
2013-02-08 22:23:58 +01:00 |
|
Sebastien Bourdeauducq
|
b092237fa6
|
xilinx_ise: support building files without running ISE
|
2013-02-08 20:31:45 +01:00 |
|
Sebastien Bourdeauducq
|
7b8e8a19f3
|
Support adding Verilog/VHDL files
|
2013-02-08 20:25:20 +01:00 |
|
Sebastien Bourdeauducq
|
32dcfc6d02
|
generic_platform: support name remapping
|
2013-02-08 18:27:46 +01:00 |
|
Sebastien Bourdeauducq
|
9ecfdeccec
|
platforms/rhino: add PCA9555 I2C expander
|
2013-02-08 17:44:13 +01:00 |
|
Sebastien Bourdeauducq
|
fef9d0fc78
|
generic_platform: fix typo
|
2013-02-08 17:43:04 +01:00 |
|
Sebastien Bourdeauducq
|
78f8ec1a53
|
platforms: add M1
|
2013-02-08 17:42:35 +01:00 |
|
Sebastien Bourdeauducq
|
25882c6c83
|
platforms: ROACH (incomplete)
|
2013-02-07 22:38:33 +01:00 |
|
Sebastien Bourdeauducq
|
fb5130fc1f
|
Initial version
|
2013-02-07 22:07:30 +01:00 |