b018fcedc4
dvisampler/chansync: set synced to 0 when control tokens do not arrive at the same time
2013-04-16 22:21:03 +02:00
1ab89d6a62
tftp.h, tftp.c: add tftp_put
2013-04-16 19:23:12 +02:00
22f39b9d26
tftp.c: use symbolic constant for block size
2013-04-16 19:23:12 +02:00
944dd5932d
tftp.c (format_request): pass opcode as argument
2013-04-16 19:23:12 +02:00
aafb3ef8d7
tftp.c: use uintNN_t instead of "unsigned short", etc.
2013-04-16 19:23:12 +02:00
cdb5519272
tftp.h, tftp.c (tftp_get): make "buffer" void and use unsigned char internally
2013-04-16 19:23:12 +02:00
effa71a811
tftp.c: make "packet_data" unsigned and optimize strcpy+strlen
2013-04-16 19:23:12 +02:00
e0e447f0e0
tftp.c (rx_callback): simplify expressions containing unnecessary casts
2013-04-16 19:23:12 +02:00
36613c7955
tftp.c: use symbolic constants for protocol opcodes
2013-04-16 19:23:12 +02:00
65b807b63f
microudp.c: avoid redundant accesses into multi-level structures
2013-04-16 19:23:11 +02:00
0d21711c1b
dvisampler/chansync: use Record.raw_bits()
2013-04-14 17:06:29 +02:00
8914969760
dvisampler/clocking: insert DCM_CLKGEN before PLL
2013-04-14 16:53:19 +02:00
f833bc9aa9
software/videomixer: use new csr.h
2013-04-14 16:33:00 +02:00
7a6e56492c
edid.py: sample SCL only every 64 clock cycles, to avoid bouncing
...
Possibly due to SCL rising fairly slowly (in the 0.5-1 us range),
bouncing has been observed while crossing the "forbidden" region
between Vil(max) and Vih(min).
By lowering the sample rate from once per system clock to once
every 64 clock cycles, we make sure we sample at most once during
the bounce interval and thus never see a false edge. (Although we
may see a rising edge one sample time late, which is perfectly
harmless.)
2013-04-12 22:48:46 +02:00
950d3a4469
framebuffer: use new flow API
2013-04-10 21:34:15 +02:00
3be20f6ae4
dfii: adapt to new Record API
2013-04-02 00:15:42 +02:00
4f4f260e76
Convert to new CSR API
2013-03-30 17:28:15 +01:00
caa19f9ab2
framebuffer: larger counters
2013-03-29 17:15:11 +01:00
7133d9abb0
m1crg: reset VGA clock generator
2013-03-29 17:14:48 +01:00
854c0461b4
framebuffer: process two pixels per system clock cycle
2013-03-28 20:46:16 +01:00
4dcec32010
top: allocate one more ASMI port to framebuffer
2013-03-28 20:46:00 +01:00
b603eaf7d4
m1crg: allow up to 150MHz pixel clock
2013-03-28 20:45:42 +01:00
8fd092ca12
crg: support VGA pixel clock reprogramming
2013-03-28 19:07:17 +01:00
1e860c7472
Use new Mibuild generic_platform API
2013-03-26 17:57:17 +01:00
1045d64e6e
framebuffer: RGBA -> ARGB
2013-03-25 18:32:25 +01:00
8ee6dab4f9
fb: better ordering of pixels within ASMI words
2013-03-25 15:56:54 +01:00
fdf7f10f54
Automatically build CSR access functions
2013-03-25 14:42:48 +01:00
6a54276d55
software/include/base: C++ compatibility
2013-03-25 14:38:58 +01:00
3640cab439
software/common.mak: add C++ definitions
2013-03-24 16:11:53 +01:00
6010308317
software/videomixer: report char position + detected resolution, detect phase at beginning
2013-03-24 00:46:23 +01:00
1333367de8
dvisampler: add resolution detection
2013-03-24 00:45:29 +01:00
ee5bfd4d3d
dvisampler/charsync: report position
2013-03-24 00:44:50 +01:00
99f9ffa7e8
dvisampler/decoding: set C to 0 during data
2013-03-24 00:44:19 +01:00
fb9a2788e8
dvisampler/charsync: fix found_control signal
2013-03-24 00:43:22 +01:00
80f3e97ca9
software/stddef.h: c++ compat for NULL
2013-03-24 00:17:42 +01:00
e06585d9fe
dvisampler: clean up EDID data
2013-03-23 13:48:40 +01:00
34b8388b45
dvisampler: decode before channel sync
2013-03-22 23:49:25 +01:00
037625886d
dvisampler: decoding
2013-03-22 21:28:17 +01:00
d65941d6cc
dvisampler: channel synchronization
2013-03-22 18:37:10 +01:00
515cdb2bd8
dvisampler: character synchronization
2013-03-21 22:56:13 +01:00
7c4ca4fd66
dvisampler/datacapture: deserialize to 10 bits
2013-03-21 19:06:15 +01:00
fa2331e084
dvisampler/clocking: generate pix reset
2013-03-21 19:02:04 +01:00
2315544b36
software/videomixer: quick hack for phase detection
2013-03-21 15:32:26 +01:00
a6a3d93059
software: add videomixer base files
2013-03-21 10:42:31 +01:00
bb566c9e7c
software/bios: change boot order
2013-03-21 10:41:56 +01:00
0a14c3714b
dvisampler: software controlled phase detector
2013-03-21 00:46:29 +01:00
28cb97068c
dvisampler/clocking: proper pix5x reset synchronization
2013-03-18 20:31:59 +01:00
5126f616fb
dvisampler: use pix5x as IODELAY clock
2013-03-18 19:03:17 +01:00
48aae9bee5
Use Instance.Input(..., ClockSignal/ResetSignal) instead of Instance.ClockPort/ResetPort
2013-03-18 17:44:01 +01:00
0c0140a8fb
m1crg: set CLKIN_PERIOD for vga_clock_gen
2013-03-17 20:16:58 +01:00
Sebastien Bourdeauducq
Werner Almesberger