2cd80990e4
minicon: fix use of phy phases
2014-11-27 22:13:17 +08:00
8418ccafdc
minicon: remove unused signals and fix indent
2014-11-27 22:12:05 +08:00
cf92821fcf
Refactor directory hierarchy of sdram phys and controllers
2014-11-27 22:09:10 +08:00
f33b285af1
Minicon: small SDRAM controller
2014-11-27 22:09:03 +08:00
ee928a8973
Wishbone DownConverter: Fix sel signal
2014-11-26 19:33:12 +08:00
4542de2c11
genlib/fsm: add NextValue to replace reg/reg_next/ce pattern
2014-11-25 17:16:21 +08:00
5801e5746b
fhdl/tools: do not attempt to rename sync clock domain if it does not exist
2014-11-21 14:51:05 -08:00
5202f89db1
ethmac/last_be: remove fake signal (fixed in Migen)
2014-11-21 14:48:17 -08:00
b7028848b2
ethmac: use new EndpointDescription API
2014-11-20 22:32:32 -08:00
eb47f458dd
flow: endpoint description structure with packetized parameter
2014-11-20 22:31:56 -08:00
f5fc4b365f
actorlib/fifo: add buffered parameter
2014-11-20 18:46:54 -08:00
33530e0921
ethmac: style/renaming
2014-11-20 18:01:48 -08:00
7eaa5f7372
targets/kc705: avoid ddrphy/ethphy address conflict
2014-11-20 17:11:57 -08:00
603c2641bb
new Ethernet MAC
2014-11-20 16:47:22 -08:00
b87ad1af63
xilinx_vivado: use REM for comment on Windows
2014-11-20 15:27:14 -08:00
866757f80e
Merge pull request #8 from jix/fix-acitorlib-fifo
...
actorlib/fifo: fix no-op assignment due to .payload omission
2014-11-16 21:48:12 -07:00
f847faf004
actorlib/fifo: fix no-op assignment due to .payload omission
2014-11-14 21:25:19 +01:00
2b7779d3b6
link: wip bfm
2014-11-12 18:20:34 +01:00
b423c1df4b
link: prepare simulation
2014-11-11 18:47:34 +01:00
64ed34b35a
clean up
2014-11-11 16:15:28 +01:00
705819f885
use new EndpointDescription
2014-11-11 14:54:54 +01:00
67aaf09b53
link: SATALinkLayer skeleton
2014-11-11 12:29:37 +01:00
294855e292
phy: use primitives dict and use only sata.std
2014-11-11 10:19:24 +01:00
30964db4a1
phy: send 2 ALIGN primitives every 256 DWORDs
2014-11-11 09:57:43 +01:00
9f2f8d279d
add hamming-code gen/check lib
2014-11-06 18:19:59 -08:00
f4d6ac8393
README: remove compiler-rt download instructions
2014-11-06 18:02:02 -08:00
09773df186
software: make compiler-rt a submodule
2014-11-06 18:00:28 -08:00
dff3a17711
mibuild/programmer: add migen folders to flash proxy search dirs
2014-11-05 23:23:22 +08:00
353e7fc13b
link: add SATALinkLayer skeleton (wip)
2014-11-04 22:55:31 +01:00
8f6354f2a3
link: improve crc_tb/ preamble_tb and increase length
2014-11-04 17:06:03 +01:00
c810009387
link: add Scrambler and testbench
2014-11-04 16:40:21 +01:00
8062298668
link: add CRC and testbench
2014-11-04 10:33:11 +01:00
7d15e91e26
vpi/ipc: fix decoding of index buffer
2014-11-04 16:57:34 +08:00
449daedab7
sata/link: add crc and scrambler C models from SATA specification
2014-11-03 18:11:14 +01:00
47b5ff5e33
move code and create a directory for each layer
2014-11-03 17:38:12 +01:00
ccc9a0d334
test/test_size: fix slice comparison
2014-11-03 12:08:43 +08:00
dcedc4e6a5
actorlib/structuring/Pipeline: make 'busy' a signal
2014-11-01 21:48:02 +08:00
33c3a927c2
actorlib/structuring: add Pipeline
...
Pipeline enables easy cascading of dataflow modules.
DataFlowGraph can eventually use it to implement the
add_pipeline method to avoid duplicating things.
2014-11-01 21:47:00 +08:00
8db549a23d
actorlib/structuring: add Converter
...
Converter enables easy conversions of data width on dataflows.
It handles the 3 possibles cases:
- downconverter
- upconverter
- direct connection when data width are identical.
2014-11-01 21:43:52 +08:00
a7e4907724
Merge branch 'master' of github.com:m-labs/migen
2014-11-01 21:33:35 +08:00
bd1d456f5d
flow/actor, actorlib/structuring: add packet support
2014-11-01 21:22:46 +08:00
4d1b6da42f
bus/csr: add configurable address_width (needed more than 32 modules with CSR)
2014-11-01 21:22:11 +08:00
fcf2f7517c
crc: generate error asynchronously to avoid stalling the flow and simplify
2014-11-01 21:21:46 +08:00
648ab8fa7a
kc705: add Ethernet pins
2014-11-01 21:11:47 +08:00
c0c04a1878
xilinx_vivado: use .bat on Windows platforms (otherwise Vivado uses Unix scripts...)
2014-11-01 20:59:19 +08:00
51f699758c
xilinx_vivado: add hierarchical utilization report
2014-11-01 20:57:54 +08:00
a4782899f6
fhdl/verilog: fix tristate to instance connection
2014-10-29 18:18:17 +08:00
8c5c32751e
add input pipe stage option
2014-10-28 20:53:26 +01:00
25e0ccae9a
remove DRP ports (won't be used for now)
2014-10-28 11:33:15 +01:00
3f7406a937
various fixes and simplifications, SATA1 & SATA2 OK
2014-10-28 02:15:19 +01:00
Sebastien Bourdeauducq
Yann Sionneau
Florent Kermarrec
Jannis Harder
Guy Hutchison