d3560e5772
liblitedram/sdram.c: Update sdram_write_read_check_test_pattern with SDRAM_PHY_ECP5DDRPHY.
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The return value has been changed and also required to be update for SDRAM_PHY_ECP5DDRPHY.
2021-05-25 10:28:56 +02:00
8085cc3c97
Merge pull request #915 from zyp/liblitespi_remove_mode
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software/liblitespi: Remove manual mode control.
2021-05-25 08:41:13 +02:00
c06bd2c77d
Make the [ID]TLB size configurable from Litex ; expand the DTS to include cache/TLB/topology in CPUs & generate the required information for VexRiscv
2021-05-23 03:15:02 -04:00
5e40709cbc
README.md: IRC channel moved to moved to irc.libera.chat ( https://libera.chat ) #litex due to staff issues.
2021-05-22 12:15:24 +02:00
55344b4c14
cores/clock/xilinx: Add power down support.
2021-05-19 22:31:35 +02:00
cbb75b852e
cores/clock/xilinx: Cosmetic cleanup on Instances.
2021-05-19 22:20:04 +02:00
12b27f961c
software/liblitedram: Fix compilation on designs without SDRAM.
2021-05-19 11:07:03 +02:00
aa2622b1f5
software/liblitedram: Add missing #ifdef SDRAM_DEBUG to fix compilation with large DRAMs.
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sdram_dbg seems to have current limitations: "At most 32 databits SDR or 16 databits DDR supported".
2021-05-18 11:36:19 +02:00
beac24b796
Merge pull request #918 from antmicro/jboc/sdram-leveling
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Attempt to improve DRAM leveling robustness
2021-05-18 10:38:25 +02:00
4886623df6
Merge pull request #917 from antmicro/jboc/sdram-dbg
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Add utilities for debugging DRAM problems
2021-05-18 10:31:33 +02:00
ccc2550426
Merge pull request #916 from antmicro/jboc/memtest-config
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Make memtest_data more configurable
2021-05-18 10:22:15 +02:00
93f357d853
soc/software/liblitedram: make leveling scores more robust by counting number of bitslips
2021-05-17 14:53:04 +02:00
50805797c6
soc/software/liblitedram: optional write latency calibration debug output
2021-05-17 14:49:30 +02:00
1f2b8621fe
soc/software/liblitedram: add sdram_debug command
2021-05-17 14:38:35 +02:00
e5c1482572
soc/software/liblitedram: add sdram debugging utilities
2021-05-17 14:19:16 +02:00
cd6f98c4c8
soc/software/liblitedram: use updated sdram_dfii_pix_X_addr interface
2021-05-17 14:11:10 +02:00
33fb48584b
soc/software/libbase: add option for read retries in memtest_data
2021-05-17 13:56:31 +02:00
d610c9da44
soc/software/libbase: limit number of errors printed when using MEMTEST_*_DEBUG
2021-05-17 13:53:32 +02:00
422c356930
software/liblitespi: Remove manual mode control.
2021-05-17 13:44:02 +02:00
b90d0bd1f7
soc/software/libbase: make memtest_data more configurable, add on_error callback
2021-05-17 13:42:44 +02:00
13979a43b7
soc/add_cpu: Fix/Simplify CFU integration.
2021-05-17 12:04:37 +02:00
d0e8de077c
soc/SoCController: Add separate fields for SoC and CPU resets.
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As discussed in #909 , in some specific cases, it can be interesting to be able
to keep the CPU in reset while the rest of the SoC is still operating (ex the
peripherals/bridges).
With theses changes, the old behaviour is preserved to do a full SoC Reset (at
the exception that writing a 1 is now mandatory) and a separate field specific
to the CPU reset is added.
The SoC Reset is a pulse (otherwise the system would be stuck in Reset) while
the CPU Reset is based on the register value (so can be pulse or hold).
2021-05-17 11:43:04 +02:00
06f4658174
cpu: Specify clock domain (improve readability).
2021-05-17 10:51:54 +02:00
78bdde0424
cpu/vexriscv: Simplify CFU integration, use Cfu.v as default CFU when not specified and rename argument to --cpu-cfu.
2021-05-17 10:02:58 +02:00
87bb10f43b
CHANGES: Start listing changes for next release.
2021-05-17 09:58:46 +02:00
a6c37df175
soc_core: Improve readability and move ROM initialization to SoCCore. (--integrated-rom-file args is also renamed to --integrated-rom-init to simplify support for str and list).
2021-05-17 09:55:28 +02:00
dd72b1acfe
soc/add_cpu: Add **kwargs support.
2021-05-17 09:53:40 +02:00
298f65e78e
cpu/vexriscv: Change methods' order to improve readability.
2021-05-17 08:54:53 +02:00
fc0e1440c5
Merge pull request #908 from antmicro/cfu-integration
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Add CFU integration
2021-05-17 08:43:38 +02:00
1571da4989
software/liblitespi: Fix speed test. ( #911 )
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Before this patch, the loop would finish with lowest_div either set to the first failing value
or 0 even if it succeeded with 0. Fix it so that if all tests pass, it’ll end up being -1 before
the incrementation.
This patch also skips retesting the original value. If the retest failed, lowest_div would be incremented past the original value and could potentially wrap around.
2021-05-17 08:30:38 +02:00
d5dab98a2c
Add CFU integration
2021-05-14 09:20:58 +02:00
53982acd9f
I2S fix: sample SYNC on the correct edge ( #904 )
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* resolve issue #862 add description to soc.svd
The issue is that with no description provided it simply would
not put out a description tag, which breaks compatibility with
other programs.
Insert a somewhat useful default description including a timestamp
and the words "LiteX SoC".
* I2S fix: sample SYNC on the correct edge
The original Tx path implementation samples SYNC on the falling
edge, out of convenience with the fact that teh data must also
change on the falling edge.
This works OK, until you have a CODEC which has a ~40ns max
delay spec on the SYNC, and also has a slightly asymmetric
SYNC edge (the SYNC signal is also the WCLK or LRCLK depending on
which docs you read). The SYNC by spec is supposed to change
on the falling edge, and this extra delay is enough to cause
the SYNC to introduce occassional bit or frame shifts into
the audio.
This fix samples the SYNC on the rising edge, but still
changes the data on the falling edge, thus allowing for
implementations where SYNC has quite loose timings relative
to everything else (as is the case on the TLV320AIC3200)
2021-05-07 08:17:49 +02:00
01a7ff44d2
Merge pull request #905 from hansfbaier/master
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lattice/programmer.py: Add iCESugar programmer
2021-05-07 08:16:55 +02:00
5fd1cae618
lattice/programmer.py: Add iCESugar programmer
2021-05-07 10:55:48 +07:00
34ed5672c3
tools/litex_server/litex_term: Add --jtag-chain argument.
2021-05-06 15:41:25 +02:00
24105f12d5
openocd/stream: Expose chain parameter.
2021-05-06 15:25:18 +02:00
aea1e7fb20
jtag/jtagbone: Expose chain parameter.
2021-05-06 14:58:47 +02:00
3ce5f3867a
cores/video/VideoS7GTPHDMIPHY: Add refclk support (None, Differential or Single-Ended).
2021-05-06 10:50:29 +02:00
bfb90f5625
soc/cores/video: Add VideoS7GTPHDMIPHY (7-Series HDMI PHY over GTPs).
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Validated on Decklink Mini 4K Monitor at 1080p60 (should allow UHD/4K), still
some fixed things, but should provide a good basis to go further...
2021-05-05 18:12:10 +02:00
d6084cd1f9
CHANGES: Add 2021.04 changes.
2021-05-03 11:59:42 +02:00
1d21a90076
software/liblitespi: Fix compilation warning.
2021-05-03 10:34:45 +02:00
c3f4da4376
Merge pull request #902 from tcal-x/radiant-lse
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Add 'lse' as a --synth-mode alternative with Radiant toolchain.
2021-05-03 10:13:52 +02:00
dcd13d27ef
Add 'lse' as a --synth-mode option with Radiant.
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Signed-off-by: Tim Callahan <tcal@google.com>
2021-05-01 21:12:56 -07:00
fb8f45be73
Merge pull request #901 from stffrdhrn/litex-sdcard-irq
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integration/soc: Wire up the sdirq to the CPU
2021-04-30 12:30:35 +02:00
59b968decc
cores/clock/gowin_gw1n: Fix indent.
2021-04-30 12:22:59 +02:00
5dc3ad3b29
soc/cores/spi/SPISlave: Minor cleanup.
2021-04-30 12:16:49 +02:00
75bb78a413
cores/clock: Add initial Gowin GW1N PLL support.
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For now limited to one output clock and not supporting phase/duty cycle adjustements.
2021-04-30 11:31:04 +02:00
fefc5aae66
cores/video/VideoVGAPHY: Add optional clk support.
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Some LCDs displays are almost VGA compatible (no DE, active low hsync/vsync)
but require the clock.
2021-04-29 11:50:04 +02:00
87ebdea5a7
software/libliteeth: Add optional ETH_PHY_NO_RESET support to allow disabling software reset.
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Un-wanted when using the Hybrid LiteETHMAC since interrupt the hardware UDP/IP stack.
2021-04-29 11:50:00 +02:00
a9e935e61a
tools/litex_json2dts: Add interrupt settings for sdcard
2021-04-29 17:52:17 +09:00
Florent Kermarrec
Romain Dolbeau
Jędrzej Boczar
Vegard Storheil Eriksen
Robert Szczepanski
bunnie
Hans Baier
Tim Callahan
Stafford Horne