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676 Commits 42 Branches 14 Tags 30 MiB
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676 Commits

Author SHA1 Message Date
Sebastien Bourdeauducq 5dc875de69 UART: use new bank API and event manager 2012-02-06 17:45:31 +01:00
Sebastien Bourdeauducq 45529d5941 BIOS: hello world 2012-02-05 20:01:28 +01:00
Sebastien Bourdeauducq 33da32417a Update gitignore 2012-02-05 20:01:14 +01:00
Sebastien Bourdeauducq 9b9a510525 Memory map 2012-02-05 19:54:08 +01:00
Sebastien Bourdeauducq 17cd8dd479 Add tools 2012-02-05 19:14:24 +01:00
Sebastien Bourdeauducq e2317bc83b flash: remove splash screens 2012-02-05 19:12:33 +01:00
Sebastien Bourdeauducq 1ad44b6571 software: dependencies the Werner way 2012-02-03 12:25:55 +01:00
Sebastien Bourdeauducq 1a4a6eb445 Copy some software code from the original Milkymist SoC. 
Libbase should keep its RAM usage to a minimum as it is meant to
be executed before the SDRAM is up and running. (Having lots of
code is OK though as we XIP from the flash)
 2012-02-03 12:08:17 +01:00
Sebastien Bourdeauducq b5cb1083ab sram: fix WE signal 2012-02-03 10:38:17 +01:00
Sebastien Bourdeauducq 8a2646a549 Remove explicit bus names 2012-01-27 22:21:08 +01:00
Sebastien Bourdeauducq 28f00c3a9a Add on-chip SRAM 2012-01-27 22:09:03 +01:00
Sebastien Bourdeauducq 6fde54c5aa Use meaningful class names 2012-01-21 12:25:22 +01:00
Sebastien Bourdeauducq f6aa95a4d0 Use new verilog.convert API 2012-01-20 23:00:11 +01:00
Sebastien Bourdeauducq f8d5c27ef8 Wishbone: omit fixed LSBs 2012-01-13 17:28:58 +01:00
Sebastien Bourdeauducq 570ea8ccf8 convtools -> tools 2012-01-13 17:07:46 +01:00
Sebastien Bourdeauducq b60abfaa4a Convert -> convert 2012-01-05 19:27:45 +01:00
Sebastien Bourdeauducq 3b640c45bb Use new syntax 2011-12-18 22:02:05 +01:00
Sebastien Bourdeauducq 6664af73d1 uart: new design using FHDL and bank (TX only, incomplete) 2011-12-18 00:29:37 +01:00
Sebastien Bourdeauducq bb21f7584a 32-device, 8-bit CSR bus 2011-12-17 15:54:42 +01:00
Sebastien Bourdeauducq 1b3edd07ca norflash tb: use get_fragment 2011-12-17 15:22:26 +01:00
Sebastien Bourdeauducq 0e30d67fa3 Multiply system clock 2011-12-17 15:00:18 +01:00
Sebastien Bourdeauducq 85fbe07b94 clkfx module 2011-12-17 15:00:11 +01:00
Sebastien Bourdeauducq 411e1af980 Proper reset generation 2011-12-16 22:25:26 +01:00
Sebastien Bourdeauducq 738b45dcbd Support the new FHDL syntax 2011-12-16 21:30:22 +01:00
Sebastien Bourdeauducq ca68097ef6 Pay a bit more attention to PEP8 2011-12-16 16:02:49 +01:00
Sebastien Bourdeauducq b487e99bcf Initial import 2011-12-13 17:33:12 +01:00