Sebastien Bourdeauducq
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1eb348c573
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fhdl: do not attempt slicing non-array signals to keep Verilog happy
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2012-02-06 18:07:02 +01:00 |
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Sebastien Bourdeauducq
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629e771fc0
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fhdl/structure: binary constant builder
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2012-02-05 19:32:11 +01:00 |
Lars-Peter Clausen
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2b3f00cbc1
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fhdl/namer: Add support for STORE_DEREF opcode
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
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2012-02-02 21:15:10 +01:00 |
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Sebastien Bourdeauducq
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6a9b59786b
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fhdl/namer: extract variable names with bytecode inspection
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2012-01-28 23:17:44 +01:00 |
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Sebastien Bourdeauducq
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5c2df45577
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fhdl: do not prefix instance signal names
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2012-01-28 11:39:28 +01:00 |
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Sebastien Bourdeauducq
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685b5eb08f
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fhdl: support memory read enable
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2012-01-27 21:39:23 +01:00 |
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Sebastien Bourdeauducq
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0cc7e2ac1e
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fhdl: make WRITE_FIRST default
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2012-01-27 21:35:58 +01:00 |
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Sebastien Bourdeauducq
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5405a83ff9
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fhdl: memories working
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2012-01-27 20:22:17 +01:00 |
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Sebastien Bourdeauducq
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a5bd111370
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fhdl/verilog: clean up signal classification and support memory descriptions
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2012-01-27 16:54:48 +01:00 |
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Sebastien Bourdeauducq
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6b1d775e9f
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fhdl/structure: memory description
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2012-01-27 16:53:34 +01:00 |
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Sebastien Bourdeauducq
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d3d5b481fe
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Include fragment pads in pre-naming dictionary
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2012-01-20 22:59:40 +01:00 |
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Sebastien Bourdeauducq
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039c6d8eb4
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namer/trace_back: behave on None code_context
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2012-01-20 22:52:50 +01:00 |
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Sebastien Bourdeauducq
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e9be3241f6
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Fix instance support
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2012-01-20 22:36:17 +01:00 |
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Sebastien Bourdeauducq
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e4f531a739
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Include unused I/Os in pre-naming dictionary and register signals with name_override
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2012-01-20 22:20:32 +01:00 |
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Sebastien Bourdeauducq
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904d14d4cf
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Remove NoContext
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2012-01-20 22:15:44 +01:00 |
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Sebastien Bourdeauducq
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05b20d4987
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Only include context prefix when necessary
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2012-01-19 19:25:04 +01:00 |
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Sebastien Bourdeauducq
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fc473e31eb
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Fix disjoint namespace test
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2012-01-19 19:24:43 +01:00 |
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Sebastien Bourdeauducq
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00d3eb7989
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Always include last step in names
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2012-01-19 18:42:43 +01:00 |
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Sebastien Bourdeauducq
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4eac60d181
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New naming system: second attempt
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2012-01-19 18:25:25 +01:00 |
|
Sebastien Bourdeauducq
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bdde97f5fd
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New naming system beginning to work
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2012-01-16 18:42:55 +01:00 |
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Sebastien Bourdeauducq
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ab8e08a2ed
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fhdl: new naming system (broken)
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2012-01-16 18:09:52 +01:00 |
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Sebastien Bourdeauducq
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aa8b8da684
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fhdl: allow None statements
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2012-01-15 17:45:54 +01:00 |
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Sebastien Bourdeauducq
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3c7161cc34
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flow: saner endpoint management
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2012-01-15 15:09:44 +01:00 |
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Sebastien Bourdeauducq
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b06e70d849
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corelogic: FSM
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2012-01-09 16:28:48 +01:00 |
|
Sebastien Bourdeauducq
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34c69db14a
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endpoint: add _i/_o suffix on signal names
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2012-01-07 21:21:46 +01:00 |
|
Sebastien Bourdeauducq
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cdd9977a40
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fhdl: better signal naming heuristic
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2012-01-07 15:30:14 +01:00 |
|
Sebastien Bourdeauducq
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b6763c28ea
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constant: equality
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2012-01-07 12:29:47 +01:00 |
|
Sebastien Bourdeauducq
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7b395b565e
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verilog: split comb block, use assign statements
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2012-01-07 12:19:06 +01:00 |
|
Sebastien Bourdeauducq
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f209bf6b33
|
convtools -> tools
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2012-01-07 00:39:28 +01:00 |
|
Sebastien Bourdeauducq
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3c1dada9cf
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record: compatibility check
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2012-01-06 23:00:23 +01:00 |
|
Sebastien Bourdeauducq
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d7a3bed44c
|
Signal repr
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2012-01-06 11:20:33 +01:00 |
|
Sebastien Bourdeauducq
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9366a226bb
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Convert -> convert
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2012-01-05 19:27:33 +01:00 |
|
Sebastien Bourdeauducq
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76db20cd9f
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fhdl: encapsulate replicated constants
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2011-12-23 00:35:13 +01:00 |
|
Sebastien Bourdeauducq
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8a394f9159
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verilog: comb reset
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2011-12-22 00:04:53 +01:00 |
|
Sebastien Bourdeauducq
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4d6be55e9f
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verilog: break down Convert function
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2011-12-21 23:08:50 +01:00 |
|
Sebastien Bourdeauducq
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26e0b817e8
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verilog: ignore variable property in combinatorial block
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2011-12-21 23:00:36 +01:00 |
|
Sebastien Bourdeauducq
|
7456195775
|
Consistent names
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2011-12-21 22:57:07 +01:00 |
|
Sebastien Bourdeauducq
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4f4d809a4e
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fhdl: better matching of assignment
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2011-12-18 21:49:48 +01:00 |
|
Sebastien Bourdeauducq
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dd42b2daff
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fhdl: also take into account object attributes in _make_signal_name. Get rid of declare_signal
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2011-12-18 21:47:29 +01:00 |
|
Sebastien Bourdeauducq
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41e2430e2b
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fhdl: automatic signal name from assignment
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2011-12-18 21:26:51 +01:00 |
|
Sebastien Bourdeauducq
|
d21e095397
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fhdl: fix series of if/elif/else
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2011-12-17 20:31:42 +01:00 |
|
Sebastien Bourdeauducq
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6f8a6db40a
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verilog: get the simulator to run the combinatorial process at the beginning
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2011-12-17 15:20:22 +01:00 |
|
Sebastien Bourdeauducq
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ec47394012
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verilog: support for float parameters in instances
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2011-12-17 14:59:27 +01:00 |
|
Sebastien Bourdeauducq
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ee6ca729a2
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verilog: user-definable reset and clock
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2011-12-16 22:25:05 +01:00 |
|
Sebastien Bourdeauducq
|
c7b9dfc203
|
fhdl: simpler syntax
|
2011-12-16 21:30:14 +01:00 |
|
Sebastien Bourdeauducq
|
39b7190334
|
Pay a bit more attention to PEP8
|
2011-12-16 16:02:55 +01:00 |
|
Sebastien Bourdeauducq
|
c840848dba
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verilog: use blocking assignment in combinatorial process
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2011-12-13 14:09:12 +01:00 |
|
Sebastien Bourdeauducq
|
a72faaecdd
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fhdl: allow a namespace to be specified for Verilog conversion
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2011-12-13 00:24:40 +01:00 |
|
Sebastien Bourdeauducq
|
eee6980a36
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fhdl: support Constant parameters for Verilog conversion
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2011-12-11 20:17:51 +01:00 |
|
Sebastien Bourdeauducq
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dafef5d744
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fhdl: fix list references (thanks Lars)
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2011-12-11 20:17:29 +01:00 |