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9644 Commits

Author SHA1 Message Date
Florent Kermarrec 1aee3ba72e cores/cpu/ibex: Remove patch (no longer required). 2021-11-05 17:19:17 +01:00
Florent Kermarrec 2740dd34e7 sim/verilator: Revert regular_comb change and just pass it to get_verilog as before. 2021-11-05 16:27:38 +01:00
Florent Kermarrec 67431f4109 cores/led: Add initial WS2812/NeoPixel core (MMAPed). 2021-11-04 08:41:00 +01:00
enjoy-digital c13be522ce
Merge pull request #1094 from mkj/matt/sim-regular-comb 
litex_sim: Allow regular_comb=False argument
 2021-11-02 15:04:42 +01:00
Matt Johnston 1716e37809 litex_sim: Allow regular_comb=False argument 
This was removed in
3b78fd928d fhdl/verilog: Remove blocking_assign (not used with LiteX).

However that breaks litedram gen.py which passes regular_comb=False
to all toolchain builders
 2021-11-02 18:16:28 +08:00
Florent Kermarrec 9ecb1e61a9 fhdl/verilog: Fix sig.direction regression. 2021-10-31 23:40:11 +01:00
enjoy-digital 3ba5d6f187
Merge pull request #1093 from cr1901/ccache 
Add option in Makefile for (s)ccache support.
 2021-10-30 22:49:32 +02:00
enjoy-digital 1eaece22d3
Merge pull request #1092 from enjoy-digital/verilog-dev 
fhdl/verilog: Improve code presentation.
 2021-10-30 22:48:21 +02:00
enjoy-digital e9dd07006e
Merge pull request #1091 from enjoy-digital/memory-dev 
fhdl/memory: Improve generation code and avoid specific generation for Efinix FPGAs.
 2021-10-30 22:47:59 +02:00
Florent Kermarrec 28c8436e01 fhdl/memory/write: Avoid slicing data when memory.width == port.we_granularity. 2021-10-30 22:42:55 +02:00
William D. Jones 86ef4e95a5 Add option in Makefile for (s)ccache support. 2021-10-29 21:04:05 -04:00
Florent Kermarrec 942e50b992 fhdl/verilog: Improve code presentation. 
- Add a LiteX Header/Trailer.
- Add _print_signal function.
- Add more infos to the Header.
- Add separators between blocks of code.
- Align Wire/Reg definition.
 2021-10-28 20:14:35 +02:00
Florent Kermarrec 08a9392c54 fhdl/memory: Simplify Read Logic. 2021-10-28 14:34:52 +02:00
Florent Kermarrec 576bb67332 fhdl/memory: Simplify Write Logic (Avoid specific cases on write granuarity). 2021-10-28 14:19:35 +02:00
Florent Kermarrec d86cd94c71 efinix/memory: Avoid specific memory_efinix generator by applying FullMemoryWE on the design. 2021-10-28 12:11:40 +02:00
Florent Kermarrec 3d4e45145d fhdl/memory: Simplify logic generation and improve intermediate address/data register naming. 2021-10-28 11:25:53 +02:00
Florent Kermarrec 95e5f20bd8 fhdl/memory: Simplify Write Logic generation when with granularity. 2021-10-28 11:11:09 +02:00
Florent Kermarrec b6c4f6ae24 fhdl/memory: Add initial Memory description. 
Gives an overview of the generated Verilog Memory, will be useful for debug/improve inference.
 2021-10-28 10:51:58 +02:00
Florent Kermarrec 71f8fc7cb5 fhdl/memory: First Cleanup/Re-organization pass. 
- Reorganize a bit (move Memory initialization to Memory declaration block).
- Use f-strings.
- Add separators.
- Add comments.
 2021-10-28 10:07:13 +02:00
enjoy-digital 70c5be6fb8
Merge pull request #1090 from gregdavill/jtag_ecp5_fix 
soc.jtag.ecp5: Support all ECP5 devices
 2021-10-27 14:34:30 +02:00
Greg Davill 5faddcdb50 soc.jtag.ecp5: Support all ECP5 devices 
- "LFE5UM" devices exclude these without serdes
 2021-10-27 20:36:31 +10:30
Florent Kermarrec 296688b2d8 cores/jtag/ECP5JTAG: Fix LUT4's INIT to create a buffer instead of inverter, thanks @gregdavill. 
Avoid restriction to even number for tck_delay_luts.
 2021-10-27 11:01:09 +02:00
Florent Kermarrec 0b40d78b0d cores/jtag/ECP5JTAG: Delay TCK with LUT4 to avoid sys_clk/jtag_clk relationship and support higher jtag_clk frequencies. 
Tested succesfully on the ButterStick with 75MHz sys_clk/25MHz jtag_clk.

Current tck_delay_luts is abritrary and should probably be adjusted.
 2021-10-26 19:59:02 +02:00
Florent Kermarrec 16af95e424 cores/jtag/ECP5JTAG: Minor cleanup, add Gabriel to copyrights (#797). 2021-10-26 18:07:09 +02:00
enjoy-digital d4ee5d1399
Merge pull request #1087 from gregdavill/jtag-ecp5 
Add JTAG support on ECP5
 2021-10-26 18:00:50 +02:00
Florent Kermarrec 12d53790a9 test/test_cpu: Prepare microwatt/lm32 test. 
microwatt: Still requires Yoys/GHDL-Synth installation.
lm32: Still requires prebuilt toolchain.
 2021-10-26 16:37:38 +02:00
enjoy-digital ccef999772
Merge pull request #1088 from enjoy-digital/ci-openrisc 
CI: Add OpenRISC GCC toolchain installation.
 2021-10-26 16:30:56 +02:00
Florent Kermarrec e617f52e34 test/test_cpu: Comment test_mor1kx for now (test work but issue seems related to the pre-built toolchain). 2021-10-26 16:30:02 +02:00
Florent Kermarrec 07b856d01e cores/cpu/mor1kx: Fix gcc_triple (Was duplicated). 2021-10-26 16:06:10 +02:00
Florent Kermarrec 5e2db8e712 README: Update installation instruction (still work with previous ones but just to encourage users to switch). 2021-10-26 15:50:40 +02:00
Florent Kermarrec cb9f0fb1b0 ci/test_cpu: Install OpenRISC GCC toolchain in CI and add mor1kx to test_cpu. 2021-10-26 15:45:43 +02:00
Florent Kermarrec f6562195d5 litex_setup: Make compat_args optional, fix dev mode. 2021-10-26 15:16:43 +02:00
Florent Kermarrec dab4845c9b litex_setup: Handle download of PowerPC/OpenRisc GCC toolchains. 2021-10-26 15:11:28 +02:00
Florent Kermarrec 71b319eeaf litex_setup: Switch to argparse and handle retro-compatibility. 2021-10-26 14:37:08 +02:00
Greg Davill bd65cf6b30 soc.cores.jtag: Add ECP5JTAG 2021-10-26 22:36:23 +10:30
Florent Kermarrec e26904bd98 README: Add LiteSPI/LiteHyperBus. 2021-10-26 12:45:15 +02:00
Florent Kermarrec e3b5734cb1 litex_setup: Add common gcc_toolchain_download function and use it to download the different toolchains. 2021-10-26 12:40:43 +02:00
Florent Kermarrec 152bbd67ed ci: GITHUB_ACTIONS export not currently required. 2021-10-26 12:24:56 +02:00
Florent Kermarrec 81da5c1bb6 ci: Increase similarities with LiteDRAM CI. 2021-10-26 12:15:13 +02:00
Florent Kermarrec d6ce5d3afa litex_setup: Fix missing repos. 2021-10-26 12:01:21 +02:00
Florent Kermarrec a6d076f810 litex_setup: Reorganize code with functions. 2021-10-26 11:36:38 +02:00
Florent Kermarrec 5c0e951dc3 litex_setup: Cleanup/Simplify. 2021-10-26 10:49:34 +02:00
Florent Kermarrec 71a91eac15 test: Rename test_boot.py to test_cpu.py. 2021-10-26 08:35:16 +02:00
Florent Kermarrec 9b4c7e8288 README/litex_setup: Remove reference to LiteVideo to encourage use of LiteX's VideoTerminal/Out core. 
LiteVideo is not longer maintained, does not have CI and is messy (code is ~10 years old where we were
still experimenting the innovative approach with Migen). The core is kept since can be useful as reference
for Video Input and for projects using it but it is not recommended for new designs.
 2021-10-26 08:21:00 +02:00
enjoy-digital 07bd8ed65b
Merge pull request #1082 from enjoy-digital/mithro-patch-1 
Fix a misspelling in README
 2021-10-26 07:51:35 +02:00
Tim Ansell a6d8679f78
Fix a misspelling 2021-10-25 17:20:48 -07:00
Florent Kermarrec 8c62bb8d2e fhdl/memory_efinix: Add efx to transformed memories to avoid conflicts. 
Fix the crash with the LiteX identifier.
 2021-10-25 19:32:18 +02:00
Florent Kermarrec 7914923d2d soc/build: Avoid no_we mode on RAMs and move specialization of Efinix memories to fhdl. 
Specialization still only support 32-bit RAMs and will still need to be refactored.
 2021-10-25 19:08:09 +02:00
Florent Kermarrec a3678c1298 build/efinix/ifacewriter: Remove add_ddr_xml (too early to support it). 2021-10-25 18:17:07 +02:00
Florent Kermarrec 0ed3803291 cores/clock/efinix_trion: Switch to excluded_ios and simplify create_clkout. 2021-10-25 18:14:45 +02:00