d905521185
build/tools/get_migen/litex_git_revision: avoid git fatal error message is not installed as a git repository
2019-11-19 09:11:11 +01:00
02bfda5e38
Merge pull request #308 from gsomlo/gls-sdram-init
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soc_sdram, bios/sdram: support sdram init for csr_data_width <= 32
2019-11-18 18:24:35 +01:00
3ef13fd27a
soc_sdram, bios/sdram: support sdram init for csr_data_width <= 32
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Enable SDRAM to be initialized when csr_data_width > 8 bits.
Currently, csr_data_width up to 32 bits is supported.
Read leveling tested with csr_data_width [8, 16, 32] on the
ecp5-versa5g and trellisboard (using yosys/trellis/nextpnr),
and on the nexys4ddr (using Vivado).
Signed-off-by: Gabriel Somlo <gsomlo@gmail.com>
2019-11-18 09:00:19 -05:00
1efb18f1ea
soc/interconnect/packet/Depacketizer: another simplifcation pass
2019-11-18 09:06:56 +01:00
af52203c00
soc/interconnect/packet/Depacketizer: cleanup "ALIGNED-DATA-COPY" state
2019-11-17 11:57:14 +01:00
8272a00d6e
soc/interconnect/packet/Depacketizer: replace no_payload with sink_d.last
2019-11-17 11:50:09 +01:00
6059712794
test/test_packet: add randomness on ready output, fix corner-cases on Packetizer/Depacketizer
2019-11-16 14:39:18 +01:00
9642893371
test/test_packet: add randomness on valid input, fix corner-cases on Packetizer
2019-11-16 08:49:04 +01:00
888fd55bd8
Merge pull request #307 from sergachev/master
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change >512 B CSR memory exception to a warning
2019-11-15 18:17:35 +01:00
2f2cfc9951
soc/interconnect/packet: fix synthesis (synthesis tools can do all sort of optimizations, but we still need to provide valid verilog :))
2019-11-15 16:19:05 +01:00
444ae951e9
change >512 B CSR memory exception to a warning
2019-11-15 15:34:12 +01:00
31661e9e2d
soc/interconnect/packet: connect error/last_be only present on both sink and source
2019-11-15 14:57:31 +01:00
2946581e50
soc/interconnect/packet: simplify/refactor Packetizer/Depacketizer to keep it simple
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To avoid complex FSMs, let the synthesis tool do the simplifications when the FSM states are not reachable.
2019-11-15 14:39:55 +01:00
33c4d961b5
test/test_packet: add 32/64/128-bit loopback tests (passing :))
2019-11-15 11:37:52 +01:00
824faf9722
test/test_packet: prepare for testing dw > 8-bit
2019-11-15 11:32:42 +01:00
86662b54d0
soc/interconnect/packet: update copyright
2019-11-15 11:25:38 +01:00
5c19b133ac
soc/interconnect/packet: add > 8-bit support to Packetizer/Depacketizer
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With high speed link (10gbps XGMII ethernet for example), stream data_width is generally
> 8-bit which make header/data un-aligned on bytes boundaries. The change allows the
Packetizer/Depacketizer to work on stream with a data_width > 8-bit.
2019-11-15 11:24:17 +01:00
5f151152ca
build/sim: cleanup run_as_root
2019-11-15 10:57:31 +01:00
446ae57b75
build/sim/modules: add XGMII 10Gbps ethernet module
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Used to simulate SoCs with XGMII 10Gbps ethernet and to do LiteEth verification
2019-11-15 10:51:55 +01:00
56fbd2f250
sim/ethernet: remove trailing whitespaces
2019-11-15 10:39:49 +01:00
442e23d7fd
test: add initial test_packet
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Use a header with 8,16,32,64,128-bit fields and test a Packetizer/Depacketizer loopback with random field values, random packet data & length.
2019-11-15 10:29:50 +01:00
eb3888f68e
tools/litex_sim: cleanup/update (no functional change)
2019-11-14 11:19:23 +01:00
4798d6b750
tools/litex_term: remove automatic reboot when flashing and clear mem_regions to avoid re-flashing on next reboot(s)
2019-11-11 18:38:10 +01:00
a17e307acf
bios/flash: minor cleanup on serialboot flashing, add flash address support
2019-11-09 00:05:36 +01:00
2d6100bdbe
Merge pull request #305 from FrankBuss/master
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adding support to flash an FBI image
2019-11-08 23:51:49 +01:00
05e8abfee3
soc_core: add integrated-rom-file parameter to allow initializing rom from command line
2019-11-08 23:32:10 +01:00
0a030fe17d
cores/code_8b10b/Decoder: add basic invalid symbols detection
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Check that we have 4,5 or 6 ones in the symbol. This does not report all
invalid symbols but still allow detecting issues with the link.
2019-11-08 19:43:01 +01:00
9857d9d9d2
adding support to flash an FBI image
2019-11-08 17:16:28 +01:00
c96f31a9ad
software/bios: rename ef command to fe (for consistency)
2019-11-08 13:14:21 +01:00
4a12a92d62
software/libbase/spiflash: rename CHIP_ERASE_CMD to CE_CMD (for consistency)
2019-11-08 13:13:54 +01:00
7fb9cfeb64
Merge pull request #302 from FrankBuss/master
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erase flash command added
2019-11-08 13:04:33 +01:00
db4739df81
soc_core: remove add_cpu method (when no real CPU but only wishbone masters, self.cpu is declared as CPUNone)
2019-11-08 12:55:29 +01:00
468df3c857
erase flash command added
2019-11-07 19:19:54 +01:00
f1714405c3
integration/export: do not include soc.h in csr.h when with_access_functions=False
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Idealy we should have another parameter for that.
2019-11-07 09:02:31 +01:00
b52dcde9ba
soc_sdram/kcu105: add optional main_ram_size_limit and use it on KCU105 to limit to 1GB instead of 2GB.
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CSR map will need to be updated to support the 2GB.
2019-11-07 09:00:54 +01:00
9053d0803a
soc_sdram: remove use_full_memory_we parameter (always used as True)
2019-11-07 08:56:52 +01:00
1b94699d12
soc_sdram: update copyrights
2019-11-07 08:44:34 +01:00
2da421f64e
Merge pull request #300 from gsomlo/gls-rocket-axi
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RFC: Direct link between Rocket/mem_axi <--> LiteDRAM dataport
2019-11-07 08:40:30 +01:00
28708f4208
cpu/rocket: parameterize axi interface data width
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Rocket variants can be configured with axi port data widths that
are multiples of the native word size (64 bits in our case). In
the future, we will add variants with mem_axi data width > 64 bit,
to match the native data width of the LiteDRAM controller on
various development boards (e.g., 128 bits on the ecp5versa, and
256 bits on the trellisboard).
Signed-off-by: Gabriel Somlo <gsomlo@gmail.com>
2019-11-01 08:55:27 -04:00
014db66444
soc_sdram: remove upper limit on usable main RAM
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Revert commit #68a503174.
2019-11-01 08:55:15 -04:00
ec831f5b63
cpu/rocket, soc_sdram: Connect mem_axi to LiteDRAM, bypass WB bus
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Connect Rocket's dedicated port for cached RAM accesses (mem_axi)
directly to the LiteDRAM data port, bypassing the shared LiteX
(Wishbone) bus.
When both Rocket's mem_axi and LiteDRAM's port have the same data
width, use a native point-to-point AXI connection.
Otherwise, convert both ends to Wishbone, and use the Wishbone
data width converter to bridge the gap.
FIXME: In the future, this part should be replaced with a native
AXI data width converter!
Signed-off-by: Gabriel Somlo <gsomlo@gmail.com>
2019-11-01 08:52:39 -04:00
9c3c43c94a
interconnect/csr_bus/SRAM: add mem_size check
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Memory size is limited to 512 bytes:
- CSR region size is 0x800 (4096)
- default csr_data_width is 8
maximum size = 4096/8 = 512 bytes.
2019-11-01 11:33:50 +01:00
edb1731ef9
soc_core/soc_core_args: specify default cpu (vexriscv)
2019-11-01 11:30:50 +01:00
cc607f022a
lattice/diamond/tcl: always use / separators, even on windows
2019-11-01 10:11:12 +01:00
59acf0ea1c
cpu/minerva: elaborate minerva verilog to build directory
2019-11-01 09:59:13 +01:00
a762d29b19
soc/integration/builder: pass output_dir to platform, make sure gateware/software directory are created before finalizing
2019-11-01 09:59:06 +01:00
855d0e925d
cpu/minerva: generate minerva.v near core.py not in submodule
2019-10-31 21:16:27 +01:00
85d6607257
cpu/minverva: give more explicit error message when not able to elaborate cpu
2019-10-31 08:52:04 +01:00
3465fc96d4
Merge pull request #297 from mithro/mem-region-pp
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Improve the error message on memory region conflict.
2019-10-30 20:49:27 -07:00
4408dad9d2
Improve the error message on memory region conflict.
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Before;
```
ValueError: Memory region conflict between rom and main_ram
```
After;
```
ValueError: Memory region conflict between rom (<SoCMemRegion 0x10000000 0x10000 cached>) and main_ram (<SoCMemRegion 0x0 0x20000000 cached>)
```
Fixes #296 .
2019-10-30 19:32:20 -07:00
Florent Kermarrec
Gabriel Somlo
Ilia Sergachev
Vamsi K Vytla
fb@frank-buss.de
Tim Ansell