db3fa1efc7
move valentyusb install to litex_setup.py
2022-06-19 12:51:14 +01:00
0941459061
integration/soc: Add initial AXI-full support.
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Main bus can now be switched to AXI-full with --bus-standard=axi.
The interconnect will be AXI-Full (Using Alex Forenchich's verilog_axi
Interconnect and Crossbar) but ROM/SRAM will still be in AXI-Lite (Will
be switched to AXI-full in the future).
This gives a first working version that can be used for further improvements.
Note that the interconnect can also be selected by --bus-interconnect=shared or
crossbar.
2022-06-17 16:21:31 +02:00
8394e93742
interconnect/axi/axi_full: Add AXI Interconnect (Shared and Crossbar).
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For now reusing Alex Forenchich's modules wrapped with LiteX.
2022-06-17 16:07:05 +02:00
bc667c6456
interconnect/axi/axi_full/AXIInterface: Add name/bursting parameters.
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To add compatibility with AXILiteInterface and allow dynamic selection.
2022-06-17 16:04:25 +02:00
333aadbf6e
integration/soc/SoC: Switch to finalize and finalize submodule only at the end.
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This avoid elaborating submodules before adding the final modules and gives more
flexibility.
2022-06-17 16:01:28 +02:00
4c0a943996
interconnect/axi: Create axi directory and split code by type/functionnality.
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AXI code is now too large to be contained in a single file, splitting code by type/functionnality
will simplify future additions.
2022-06-16 18:53:12 +02:00
c4e07e2a5b
integration/soc: Allow Bus Interconnect to use either InterconnectShared or Crossbar and add --bus-interconnect command line parameter.
2022-06-16 17:47:13 +02:00
6942e3240c
interconnect/axi/AXIDownConverter: Switch to AXI-Full (Inspired from AXIUpConverter).
2022-06-16 16:16:49 +02:00
50553a45ec
integration/soc/add_adapter: Create data_width_convert/bus_standard_convert functions and improve code genericity.
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This already cleanup/simplify code and will also allow eventual order changes in the conversions.
2022-06-16 11:53:47 +02:00
b6f4302e8e
integration/soc/add_adapter: Add AXI2AXILite and AXI2Wishbone support.
2022-06-15 19:37:04 +02:00
da5d9ecf9b
interconnect/axi: Add AXIDownConverter (through AXI-Lite) and AXIConverter.
2022-06-15 19:34:47 +02:00
ac800da43c
cpus: Make use of new automatic AXI <-> AXI-Lite/Wishbone conversion.
2022-06-15 18:15:59 +02:00
d7e599c04f
integration/soc/add_adapter: Add AXI<->Wishbone and AXI<->AXI-Lite support.
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Allow directly passing AXI interfaces to add_slave/add_master and thus simplify user code.
2022-06-15 17:58:39 +02:00
f62ba0f66d
integration/soc: Simplify add_config and use it for all config parameters.
2022-06-15 17:34:07 +02:00
1d7aa9c438
cpu/openc906: Switch to AXI-Lite instead of Wishbone and minor cleanup.
2022-06-15 16:51:50 +02:00
eebb639c12
Merge pull request #1328 from Icenowy/c906
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[WIP] soc/cores/cpu: add initial OpenC906 support
2022-06-15 11:23:14 +02:00
8fa9178716
Merge pull request #1326 from Technosystem-Labs/openocd_0_11
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Updated OpenOCD stream for expr use
2022-06-15 11:10:02 +02:00
a4de315772
Merge pull request #1329 from Icenowy/altpll-fix
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Misc fixes to Altera PLL support
2022-06-15 10:52:24 +02:00
d1a456a545
integration/export/_get_csr_addr: Add back parenthesis around CSR_BASE + X.
2022-06-14 15:03:18 +02:00
8ffabe3bcb
soc/cores/cpu: add initial OpenC906 support
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It's only boot tested in sim and build tested in Vivado now, and it
requires a FPGA > 100k LUT4 (XC7A100T currently does not fit).
The ISR code is based on Rocket one.
These Python code depends on a forked version of OpenC906 at [1].
[1] https://github.com/Icenowy/openc906/tree/fpga-optimization
Signed-off-by: Icenowy Zheng <uwu@icenowy.me>
2022-06-14 02:04:58 +08:00
6d11d1991b
build/altera: Add derive_pll_clocks to SDC file
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Quartus software wants a derive_pll_clock sentence in SDC file to enable
automatic PLL clock derivation, and by test this sentence is harmless
even when no PLL exists.
Add this sentence to to the generated SDC file.
Signed-off-by: Icenowy Zheng <uwu@icenowy.me>
2022-06-13 22:51:54 +08:00
58f9a79cf3
cores/clock/intel_common: fix N factor not get passed to ALTPLL primitive
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The N factor is currently ignored when creating ALTPLL instance.
As Quartus will internally decide N based on all dividers, just multiply
N to all clock outputs' individual divider.
Signed-off-by: Icenowy Zheng <uwu@icenowy.me>
2022-06-13 22:51:20 +08:00
49d0463394
integration/export/csr: Allow disabling CSR_BASE #define/reuse when not wanted.
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Reuse of external defined CSR_BASE has been added for some use-cases, allowing more
flexilibity but also complicating direct read of base addresses for users in csr.h.
with_csr_base_define parameter has been added, allowing disabling CSR_BASE #define/reuse
when set to False.
2022-06-09 16:39:29 +02:00
8ccfc96b1a
build/osfpga: Fix device support.
2022-06-08 18:25:50 +02:00
59ca268de9
Updated OpenOCD stream for expr use deprecation in v0.11
2022-06-08 15:07:58 +02:00
eeed11edea
build/osfpga: Remove .init workaround since fixed in toolchain.
2022-06-07 12:34:42 +02:00
24e483026d
Merge pull request #1325 from AEW2015/litex_dev
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adding JTAG support for the xcau, Xilinx Artix UltraScale+
2022-06-07 12:11:57 +02:00
9691d205b7
adding JTAG support for the xcau, Xilinx Artix UltraScale+
2022-06-07 00:45:27 -06:00
50613f74c0
Merge pull request #1323 from jevinskie/jev/feat/intel-clocking-find-best-config
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IntelClocking: Brute-force find the best PLL config.
2022-06-06 21:58:49 +02:00
d1d0f70b2e
Merge pull request #1324 from jevinskie/jev/bug/quartus-build-script-win32-fix
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Quartus: Remove bashism from win32 bat script and add shebang on Linux
2022-06-06 21:56:57 +02:00
ace1314e02
Quartus: Remove bashism from win32 bat script and add shebang on Linux
2022-06-06 11:32:36 -07:00
fa8d31b101
IntelClocking: Brute-force find the best PLL config.
2022-06-06 11:13:52 -07:00
d537e30c5a
bios/main: Add CONFIG_NO_BOOT support to allow disabling Boot sequence and minor cleanups.
2022-06-06 18:28:39 +02:00
c299a82968
Merge pull request #1321 from zeldin/vexriscv_crt_fix_2
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cpu/vexriscv: Redo csr instruction fix
2022-06-06 11:41:11 +02:00
91d79ae1da
cpu/vexriscv: Redo csr instruction fix
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Instead of enabling the zicsr extension in crt0.S, change -march to
specify that VexRISCV implements version 2.0 of I, rather than the
latest (2.1). In 2.0 the csr instructions were still part of I.
This approach has two advantages:
* It is compatible with older versions of binutils, since they do not
need to know about the new zicsr extension
* By modifying the -march in CFLAGS, csr instructions can be used in any
code (for example by the inline functions in irq.h), not just in crt0.S.
2022-06-04 13:59:51 +02:00
3f8cafeb58
test/test_cpu: Disable cva5 and enable marocchino/mor1kx.
2022-06-03 17:14:52 +02:00
c0fc342823
test/test_cpu: Simplify using subTest/lists, test more RISC-V CPUs and comments for untested CPUs.
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Also use --opt-level=O0 to reduce compilation time (execution is a bit slower but since we are only
executing the BIOS here, total test time is still reduced).
2022-06-03 16:16:21 +02:00
eab58ff0e9
software/common.mak: Remove GCC_PATH introduced by #1279 since create lots of warning with regular toolchains.
2022-06-03 15:11:01 +02:00
481857ad0a
bios/boot: Disaboe netboot_from_bin when no MAIN_RAM.
2022-06-03 14:53:15 +02:00
5c493af573
tools/litex_sim: Update/Fix --with-ethernet.
2022-06-03 14:52:48 +02:00
3ab7eaa5f7
software/common: Disable LTO since does not seems to work in all cases and cause random issues.
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LTO will have to be properly tested before being enabled.
2022-06-03 14:42:04 +02:00
b88bcd8e87
litex_setup: Bump RISC-V GCC toolchain to 10.1.
2022-06-03 14:34:01 +02:00
e0a549f8ea
integration/export: Disable riscv_zicsr workaround for now since does not seems working.
2022-06-03 13:31:59 +02:00
3acf22ff6f
cores/clock/gowin_gw2a: Fix copyrights.
2022-06-03 12:04:11 +02:00
67b415f61c
cores/clock: Add gowin_gw2a (Reusing GW1NPLL with specific vco/pfd_freq_ranges).
2022-06-03 12:01:08 +02:00
f0ea2cb0fa
clock/gowin_gw1n: Add get_vco/pfd_freq_range methods and switch to it.
2022-06-03 11:53:55 +02:00
f33ea63278
Merge pull request #1316 from gsomlo/gls-printf-warning
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software/liblitesata: address printf int size warning
2022-06-02 21:29:39 +02:00
31439f7475
software/common.mak: Shorten GCC_INSTALLATION_PATH to GCC_PATH.
2022-06-02 18:41:55 +02:00
bafae4d449
soc/integration/export: Rewrite and fix zicsr RISC-V workaround.
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- Improve regex to be more robust (Was not working with binutils from Sifive).
- Improve readability.
- Only do it for RISC-V.
- Add comments.
2022-06-02 18:39:50 +02:00
9e38dc70a4
Merge pull request #1279 from xhebox/master
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support custom toolchain
2022-06-02 18:05:51 +02:00
Ben Stobbs
Florent Kermarrec
Icenowy Zheng
Mikołaj Sowiński
Andrew E Wilson
Jevin Sweval
Dolu1990
Marcus Comstedt