83c1adbc94
soc/cores/clock/colognechip: set lock_req to 1 by default and connect locked to USR_PLL_LOCKED_STDY
2024-02-28 17:17:06 +01:00
54d19265a7
build/colognechip/platform: typo bitstream_ext -> _bitstream_ext
2024-02-28 16:12:30 +01:00
8eb5e7b6c1
soc/cores/clock/colognechip: REF_CLK/OUT_CLK: int -> str
2024-02-28 16:11:27 +01:00
cd8ad3714d
soc/interconnect/packet/Dispatcher: Add missing **kwargs.
2024-02-28 13:32:09 +01:00
42c1046323
soc/interconnect/packet: Add **kwargs to Arbiter/Dispatcher to allow specifying keep/omit parameters for connection.
2024-02-28 13:04:48 +01:00
fea3a7ebc6
cpu/naxriscv/core/git_setup: Clone submodules as recursive to prevent errors with submodules during the git checkout.
2024-02-27 15:59:44 +01:00
253d1cfb9b
build/generic_platform/ConstraintManager: Add prepend parameter to add_extension.
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In some cases, prepend is useful when we want to replace existing IOs.
2024-02-26 17:28:03 +01:00
d3ea912339
CHANGES: Update.
2024-02-22 10:24:35 +01:00
7f91baae3a
Merge pull request #1894 from mdejw/patch-1
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Send serial data to sim uart only if rx_ready is set.
2024-02-22 10:22:05 +01:00
dc229f8df9
Merge pull request #1895 from trabucayre/json2dts_linux_fill_network
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tools/litex_json2dts_linux.py: adding ip= bootarg when localip and remoteip are provided
2024-02-22 10:20:41 +01:00
a6d015a358
tools/litex_json2dts_linux.py: adding ip= bootarg when localip and remoteip are provided
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Signed-off-by: Gwenhael Goavec-Merou <gwenhael@enjoy-digital.fr>
2024-02-22 09:40:26 +01:00
0de87ce40d
Send serial data to sim uart only if rx_ready is set.
2024-02-21 22:32:49 +01:00
63f9935f17
build/sim/config: Convert periods_ps to int since otherwise too restrictive on possible frequencies generation.
2024-02-21 11:39:49 +01:00
129446dea2
test/test_wishbone: Run all Remapper tests in byte and word modes and simplify.
2024-02-21 11:20:01 +01:00
c1dad9516a
interconnect/wishbone/Remapper: Shift origin when in word mode, fixes unit-test.
2024-02-21 11:06:15 +01:00
6213fd2151
test/test_wishbone: Add Remapper unit-test for word addressing mode.
2024-02-21 11:05:35 +01:00
c0517cd1cf
interconnect/axi: Use same default parameters than wishbone.Remapper.
2024-02-20 16:58:37 +01:00
d1e73889f9
test/test_wishbone: Add wishbone.Remapper basic tests.
2024-02-20 16:51:32 +01:00
ef256c9cc2
interconnect/wishbone: Enhance Remapper to also integrate RegionsRemapper functionnality and apply operation sequentially.
2024-02-20 16:50:56 +01:00
d78dbd6935
soc/add_spi_flash: Revert PHY_FREQUENCY definition and use in BIOS.
2024-02-20 14:23:54 +01:00
03340bcf12
soc/software/liblitespi/spiflash: replace SPIFLASH_PHY_FREQUENCY by CONFIG_CLOCK_FREQUENCY (removed by commit e498a56698)
2024-02-19 06:34:26 +01:00
677443cef7
Merge pull request #1890 from rtucker85/fix_csr_merge
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Fixes for errors when attempting import of Sub-SoCs .json
2024-02-16 18:27:39 +01:00
6c8633b9a3
soc/integration/builder: add_json: fix order of parameters
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For consistancy only. This now matches load_csr_json.
Link: https://git.motec.com.au/id/Ibe2889fafc6ef48a6f217f84246de11a9555811d
2024-02-16 16:59:14 +11:00
d4c1c97cf9
soc/integration/export: fix incorrect element in get_linker_regions
2024-02-16 15:38:48 +11:00
cfbe3b028a
interconnect/wishbone/RegionsRemapper: Add default values for src_regions/dst_regions.
2024-02-13 19:13:00 +01:00
595118fd5d
interconnect/wishbone/RegionsRemapper: Connect adr by default when no remapping.
2024-02-13 18:31:05 +01:00
5ee746f178
interconnect/wishbone: Add initial RegionsRemapper to allow remapping source regions to destination regions.
2024-02-13 18:25:46 +01:00
19db80ec9b
interconnect/Remapper: Add docstring description.
2024-02-13 17:44:02 +01:00
fe0363da25
CHANGES.md: Update.
2024-02-13 16:04:13 +01:00
bd7921cda8
soc/add_master: Add region support to allow remapping.
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Allow connecting a master to a specific region of the SoC and limiting access to it.
2024-02-13 15:59:42 +01:00
36767c66b4
soc/SoCRegion: Ensure fixed indentation in __str__.
2024-02-13 14:52:29 +01:00
46a2e6fe78
Merge pull request #1887 from Dolu1990/jtag
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tools/litex_sim support for remote_bitbang (openocd)
2024-02-13 14:29:11 +01:00
89bf0fb0cf
Merge pull request #1888 from Dolu1990/reset_vector
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core/vexriscv_smp add reset vector support
2024-02-13 11:43:40 +01:00
795fa1e1fc
core/vexriscv_smp add reset vector support
2024-02-13 11:22:05 +01:00
0a315cda2d
Merge branch 'master' into jtag
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# Conflicts:
# litex/soc/cores/cpu/vexriscv_smp/core.py
2024-02-13 10:41:26 +01:00
fe37dcf6dd
tools/litex_sim now support remote_bitbang (openocd)
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soc/cores/vexriscv_smp add jtag tap support
2024-02-13 10:35:53 +01:00
f36e7d379a
CHANGES.md: Update.
2024-02-12 17:21:42 +01:00
244bc43886
soc/integration/builder: Add add_json method to allow adding exported .json from Sub-SoCs.
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Ex: builder.add_json("icebreaker_soc.json", 0x30000000, "icebreaker_soc") to import/merge
a SoC's json file from a Sub-SoC in Main-SoC.
2024-02-12 17:19:04 +01:00
38ff48a543
soc/integration/export: Add load_csr_json function to load/import .json exports.
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Useful to merge SoC/Sub-SoCs Constants/CSRs/Memory Regions.
2024-02-12 17:16:54 +01:00
1b32d8a341
soc/add_etherbone: Revert sys_clk domain renaming when ethmac is disabled.
2024-02-09 15:10:47 +01:00
afcf78f643
soc/add_etherbone: Rename ethmac parameters with ethmac suffix since related to ethmac.
2024-02-07 19:21:38 +01:00
0ed44a2c04
Merge pull request #1886 from trabucayre/etherbone_hybrid_ip_mac
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Etherbone hybrid ip mac
2024-02-07 14:15:42 +01:00
7f211048ac
soc/integration/soc/add_etherbone: adding ethernet mac address, local/remote ip as parameters, sanity check when hybrid mode and adding ip/mac constants
2024-02-07 12:49:03 +01:00
177df0b57e
soc/integration/soc: move add_ip_constant to helpers with a renaming to add_ip_address_constants, adding function to add MACADDRx constant
2024-02-07 12:44:59 +01:00
e866892798
soc/software/bios/boot: allow to override macaddr by using constant MACADDRx
2024-02-07 11:16:12 +01:00
13c57e8304
soc/integration/soc: add_etherbone/ClockDomainRenamer: keep sys connected to sys instead of eth rx
2024-02-07 07:21:35 +01:00
57bc0369c7
integration/soc/SocCSRHandler: Make supported_address_width/paging values explicit.
2024-02-05 12:57:06 +01:00
88e530d0e8
Merge pull request #1885 from smunaut/csr-paging-0x400
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soc/integration: Allow 0x400 CSR paging
2024-02-05 12:44:51 +01:00
cd1088dbe9
Merge pull request #1884 from motec-research/efinix_spi_width
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Efinix: suport spi width for passive loading
2024-02-05 12:43:30 +01:00
3127e504d3
soc/integration: Allow 0x400 CSR paging
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It's a convenient way to get more CSR locations without changing
the whole address space layout (i.e. more space for CSR).
It still leaves 256 full 32b registers in each location which
I've never encountered a device even coming close to this, so
it should be fairly safe to do.
This doesn't change the default, just allow the user to select it.
Signed-off-by: Sylvain Munaut <tnt@246tNt.com>
2024-02-05 11:45:34 +01:00
Gwenhael Goavec-Merou
Florent Kermarrec
Marcin Dawidowicz
Richard Tucker
Dolu1990
Sylvain Munaut