Sebastien Bourdeauducq
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7582b76406
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bank: fix csrgen address decoder
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2011-12-11 20:15:30 +01:00 |
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Sebastien Bourdeauducq
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05d91c7104
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bus: Wishbone to CSR bridge
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2011-12-11 15:04:34 +01:00 |
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Sebastien Bourdeauducq
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af74a89b8a
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corelogic: timeline module
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2011-12-11 01:11:13 +01:00 |
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Sebastien Bourdeauducq
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019ef16db4
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fhdl: remove broken fragment iadd
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2011-12-11 01:10:59 +01:00 |
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Sebastien Bourdeauducq
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b00581616e
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convtools: insert reset on variables
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2011-12-11 01:10:37 +01:00 |
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Sebastien Bourdeauducq
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d3127fd5d8
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autofragment: remove debug
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2011-12-10 20:48:23 +01:00 |
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Sebastien Bourdeauducq
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44f44b8a05
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fhdl: autofragment
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2011-12-10 20:47:21 +01:00 |
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Sebastien Bourdeauducq
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4b15a84505
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fhdl: fix += for empty fragment
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2011-12-10 20:47:06 +01:00 |
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Sebastien Bourdeauducq
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a49ecc4331
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fhdl: pad support in fragments
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2011-12-10 20:25:24 +01:00 |
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Sebastien Bourdeauducq
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4d1a960308
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wishbone: decoder + shared bus interconnect
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2011-12-09 13:11:52 +01:00 |
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Sebastien Bourdeauducq
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fa63cc1ec8
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fhdl: replication support
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2011-12-09 13:11:34 +01:00 |
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Sebastien Bourdeauducq
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5c7131dc86
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wishbone: arbiter
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2011-12-08 23:21:25 +01:00 |
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Sebastien Bourdeauducq
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c1041b9a5f
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simplebus: export GetSigName function
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2011-12-08 23:06:04 +01:00 |
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Sebastien Bourdeauducq
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b2bc5ad4f4
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corelogic: multimux module
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2011-12-08 23:04:34 +01:00 |
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Sebastien Bourdeauducq
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b0c5b74c22
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verilog: handle default in case statements
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2011-12-08 23:04:20 +01:00 |
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Sebastien Bourdeauducq
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512655c108
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fhdl: improve automatic signal naming
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2011-12-08 21:28:20 +01:00 |
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Sebastien Bourdeauducq
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5034af3038
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Corelogic conversion example
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2011-12-08 21:25:05 +01:00 |
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Sebastien Bourdeauducq
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62f70a54f0
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corelogic: MC divider module
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2011-12-08 21:19:40 +01:00 |
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Sebastien Bourdeauducq
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84eb964adc
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fhdl: support negation operator
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2011-12-08 21:15:44 +01:00 |
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Sebastien Bourdeauducq
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bf021efa2b
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verilog: fix unary operator conversion
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2011-12-08 21:15:24 +01:00 |
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Sebastien Bourdeauducq
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78f18ad593
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corelogic: round-robin module
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2011-12-08 21:15:02 +01:00 |
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Sebastien Bourdeauducq
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7c99e51b90
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Named buses
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2011-12-08 19:16:08 +01:00 |
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Sebastien Bourdeauducq
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5720a51dad
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wishbone: add missing SEL
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2011-12-08 19:09:32 +01:00 |
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Sebastien Bourdeauducq
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ed05ec5f6a
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instances: signal override
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2011-12-08 18:56:14 +01:00 |
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Sebastien Bourdeauducq
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c43f3da534
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Wishbone declarations
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2011-12-08 18:47:41 +01:00 |
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Sebastien Bourdeauducq
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a6b86168ce
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Simple bus base class
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2011-12-08 18:47:32 +01:00 |
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Sebastien Bourdeauducq
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1b637cea61
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Instance support
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2011-12-08 16:35:32 +01:00 |
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Sebastien Bourdeauducq
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fab02f84cb
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fhdl: fix implicit slice index
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2011-12-07 22:21:30 +01:00 |
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Sebastien Bourdeauducq
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82f77180d5
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fhdl: cleanup value bv
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2011-12-07 22:21:10 +01:00 |
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Sebastien Bourdeauducq
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0e8d894a35
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Variable conversion
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2011-12-05 22:00:06 +01:00 |
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Sebastien Bourdeauducq
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4340680704
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Cleanup
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2011-12-05 19:25:32 +01:00 |
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Sebastien Bourdeauducq
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ec51f09c98
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Case support + register bank generator
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2011-12-05 17:43:56 +01:00 |
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Sebastien Bourdeauducq
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458cfc8623
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CSR bus definitions
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2011-12-05 00:16:44 +01:00 |
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Sebastien Bourdeauducq
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5acf2e169f
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Examples folder
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2011-12-04 23:39:48 +01:00 |
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Sebastien Bourdeauducq
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e099f4d52f
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Reset insertion
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2011-12-04 22:41:50 +01:00 |
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Sebastien Bourdeauducq
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cd8544c758
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Verilog generator
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2011-12-04 22:26:32 +01:00 |
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Sebastien Bourdeauducq
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499b95a519
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Initial import, FHDL basic structure, divider example
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2011-12-04 16:44:38 +01:00 |