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9387 Commits

Author SHA1 Message Date
Gwenhael Goavec-Merou fecc0cb227 build/efinix/ifacewriter: PLL/LVDS serdes: Trion support 2023-11-17 11:50:58 +01:00
Gwenhael Goavec-Merou cbba5b46e9 build/efinix/efinity: fix 90 phase shift float -> int (yes: WHY?) 2023-11-17 11:41:00 +01:00
Gwenhael Goavec-Merou c8a9f205e0 soc/cores/clock/efinix: allowing to specify LVDS input refclk name (Trion) 2023-11-17 11:40:41 +01:00
Florent Kermarrec 4353135f02 CHANGES: Update. 2023-11-16 13:47:17 +01:00
Florent Kermarrec aa8e9dc32f integration/builder: Add bios_format/--bios-format support to allow selecting printf format and pass it to picolibc. 
Useful to printf of float/double is required.
 2023-11-16 12:38:59 +01:00
Dolu1990 6d9cacd465 core/NaxRiscv update (timing improvements) 2023-11-14 13:45:01 +01:00
Gwenhael Goavec-Merou f41ae88d1c soc/cores/clock/efinix: create_clkin: adding lvds_input optional parameter (required when used with LVDS serdes) 2023-11-14 11:34:13 +01:00
Gwenhael Goavec-Merou 7cee8e10fd build/efinix/ifacewriter: allowing PLL to have LVDS_RX as input type 2023-11-14 11:24:17 +01:00
Gwenhael Goavec-Merou 232941be24 build/efinix/ifacewriter: generate_lvds: adding missing migen import (required by generate_lvds) 2023-11-14 11:14:57 +01:00
Gwenhael Goavec-Merou bf337559fe build/efinix/ifacewriter: generate_lvds: adding LVDS serdes support (Titanium only) 2023-11-14 10:45:16 +01:00
Florent Kermarrec edc6871ace soc/software: Rename NR_IRQ to CONFIG_CPU_INTERRUPTS. 2023-11-13 09:14:57 +01:00
Florent Kermarrec d7253ffd0e integration/soc/add_etherbone: Rename ethernet parameter to with_ethmac and minor cosmetic cleanups. 2023-11-13 08:57:22 +01:00
enjoy-digital 2d9a268ff3
Merge pull request #1838 from motec-research/etherbone 
Hybrid Etherbone simplification
 2023-11-13 08:48:29 +01:00
Gwenhael Goavec-Merou a18537bf50 build/gowin/common: disable Tristate (uncorrect code with tangNano9k hypperram #1833) 2023-11-13 06:34:59 +01:00
AndrewD 968bd28d8b
Merge pull request #1815 from motec-research/irq_attach 
soc/software: add irq_attach() / irq_detach()
 2023-11-13 14:30:48 +11:00
Andrew Dennison 737ced8fa6 soc/software: add irq_attach() / irq_detach() 
cleaner mechanism for other software to use interrupts
 2023-11-13 12:07:35 +11:00
Andrew Dennison 885d5b9cb1 tools/litex_sim: update hybrid etherbone integration 2023-11-13 11:13:19 +11:00
Andrew Dennison fb5512f6d5 soc/integration/soc: simplify hybrid etherbone 2023-11-13 11:13:10 +11:00
Florent Kermarrec 77ca872b3b tools/litex_sim: Update Etherbone/Ethernet hybrid mode integration. 2023-11-10 19:13:35 +01:00
Florent Kermarrec 57782309a2 integration/soc/add_etherbone: Exclude MAC from CSRs when in hybrid board since added externally. 2023-11-10 18:59:28 +01:00
Florent Kermarrec 9f88137ab6 remote/etherbone: Set default addr_size of 32 (To avoid breaking old code). 2023-11-10 16:13:43 +01:00
Florent Kermarrec 52adf240f9 remote/etherbone/EtherbonePacket: Set default addr_width of 32 (To avoid breaking old code using EtherbonePacket()). 2023-11-10 13:17:21 +01:00
Florent Kermarrec 5672a9dd2a CONTRIBUTORS: Update. 2023-11-10 10:35:49 +01:00
Florent Kermarrec 639c899838 CHANGES.md: Update. 2023-11-10 10:27:37 +01:00
Florent Kermarrec c419706856 CHANGES: Update. 2023-11-09 15:24:40 +01:00
Florent Kermarrec 9b4df14ab1 build/gowin/common/GowinTristate: Remove print. 2023-11-09 14:55:46 +01:00
Florent Kermarrec 48a1b2634c cores/video/VideoHDMIPHY: Fix when multiple drive_pols. 2023-11-09 13:45:27 +01:00
Florent Kermarrec 55bb9b9c56 integration/soc/bus_addressing_convert: Fix interface<->adapted_interface connection. 2023-11-09 13:06:43 +01:00
enjoy-digital d2441c6a75
Merge pull request #1833 from trabucayre/tangMega138k 
Tang mega138k
 2023-11-09 11:49:32 +01:00
Florent Kermarrec f9dc8e8564 integration/soc/bus_addressing_converter: Handle missing cases. 
- m2s: byte to word/word to byte.
- s2m: byte to word/word to byte.
 2023-11-09 11:41:54 +01:00
Florent Kermarrec 1282708a08 cpu/naxriscv/core: Cosmetic cleanups. 2023-11-09 11:40:16 +01:00
Florent Kermarrec 4ba3ad5409 sim/gtkwave: Update/fix SignalNamespace import (And make it public in fhdl/namer). 2023-11-09 10:29:43 +01:00
Florent Kermarrec 4b9c866d76 integration/soc/bus_addresing_convert: Simplify and skip on AXI/AXI-Lite interface since already handled in bridges. 2023-11-09 10:22:22 +01:00
Florent Kermarrec 03a0739d13 integration/soc/add_adapter: Use bus_ prefix for all converter functions for consistency. 2023-11-09 10:08:46 +01:00
Florent Kermarrec 53e458f63a integration/soc: Fix addressing order and remove limitations, we are now just limited to Wishbone. 2023-11-09 09:21:53 +01:00
Gwenhael Goavec-Merou 1ab85631b8 tools/litex_server, tools/remote/comm_udp: fix Etherbonexx constructors by passing addr_width/add_size 2023-11-09 07:07:48 +01:00
Florent Kermarrec 4610713797 gen/fhdl/verilog: Ensure top is not None to build hierarchy. 2023-11-08 16:58:23 +01:00
enjoy-digital 862a0dbbbf
Merge pull request #1829 from enjoy-digital/kianv 
cores/cpu: Add KianV CPU (RV32IMA) initial support.
 2023-11-08 11:43:07 +01:00
Florent Kermarrec 6598fe9c12 cores/cpu: Add KianV CPU (RV32IMA) initial support. 
litex_sim --cpu-type=kianv:

        __   _ __      _  __
       / /  (_) /____ | |/_/
      / /__/ / __/ -_)>  <
     /____/_/\__/\__/_/|_|
   Build your hardware, easily!

 (c) Copyright 2012-2023 Enjoy-Digital
 (c) Copyright 2007-2015 M-Labs

 BIOS built on Nov  8 2023 11:14:03
 BIOS CRC passed (6984e675)

 LiteX git sha1: c1e4b3a8

--=============== SoC ==================--
CPU:		KianV-STANDARD @ 1MHz
BUS:		WISHBONE 32-bit @ 4GiB
CSR:		32-bit data
ROM:		128.0KiB
SRAM:		8.0KiB


--============== Boot ==================--
Booting from serial...
Press Q or ESC to abort boot completely.
sL5DdSMmkekro
Timeout
No boot medium found

--============= Console ================--

litex> ident
Ident: LiteX Simulation 2023-11-08 11:14:00
litex>
 2023-11-08 11:37:22 +01:00
Gwenhael Goavec-Merou 93ce42f781 build/gowin/gowin: rework constraints: IOStandard & Misc in one line, merge _p/_n and only write _p 2023-11-07 20:44:37 +01:00
Gwenhael Goavec-Merou a0cb436467 build/gowin/common: adding Tristate support 2023-11-07 20:15:07 +01:00
Florent Kermarrec c1e4b3a850 xilinx/clock: Add reset_buf parameter to allow using a buffer to route reset signal. 2023-11-07 13:21:16 +01:00
enjoy-digital d0bb837b7c
Merge pull request #1828 from enjoy-digital/verilog_improvements_2 
Verilog improvements.
 2023-11-07 09:03:40 +01:00
Florent Kermarrec 657252c573 gen/fhdl/namer: Update copyrights. 2023-11-06 17:55:54 +01:00
Florent Kermarrec 5b989bcb0e gen/fhdl/verilog: Switch Assign/Operator types to IntEnum. 2023-11-06 17:24:03 +01:00
Florent Kermarrec 33fd7742c9 interconnect/stream/ClockDomainCrossing: Use DUID for clock_domain id to allow deterministic builds. 2023-11-06 16:49:54 +01:00
Florent Kermarrec ef4235a5d9 gen/fhdl/namer: Use _ for private functions and remove build_namespace. 2023-11-06 16:21:33 +01:00
Florent Kermarrec af508fddc5 gen/fhdl/namer: Improve/Simplify SignalNamespace.get_name method. 2023-11-06 15:54:19 +01:00
Florent Kermarrec 9ce29224a1 gen/fhdl/namer: Add all_numbers to HierarchyNode to avoid hasattr use. 2023-11-06 15:36:08 +01:00
Florent Kermarrec 3df23a27f5 gen/fhdl/namer: Avoid deep level of nesting on build_signal_name_dict_for_group. 2023-11-06 13:56:25 +01:00