Sebastien Bourdeauducq
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dd42b2daff
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fhdl: also take into account object attributes in _make_signal_name. Get rid of declare_signal
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2011-12-18 21:47:29 +01:00 |
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Sebastien Bourdeauducq
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41e2430e2b
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fhdl: automatic signal name from assignment
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2011-12-18 21:26:51 +01:00 |
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Sebastien Bourdeauducq
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d21e095397
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fhdl: fix series of if/elif/else
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2011-12-17 20:31:42 +01:00 |
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Sebastien Bourdeauducq
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6f8a6db40a
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verilog: get the simulator to run the combinatorial process at the beginning
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2011-12-17 15:20:22 +01:00 |
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Sebastien Bourdeauducq
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ec47394012
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verilog: support for float parameters in instances
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2011-12-17 14:59:27 +01:00 |
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Sebastien Bourdeauducq
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ee6ca729a2
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verilog: user-definable reset and clock
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2011-12-16 22:25:05 +01:00 |
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Sebastien Bourdeauducq
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c7b9dfc203
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fhdl: simpler syntax
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2011-12-16 21:30:14 +01:00 |
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Sebastien Bourdeauducq
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39b7190334
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Pay a bit more attention to PEP8
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2011-12-16 16:02:55 +01:00 |
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Sebastien Bourdeauducq
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c840848dba
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verilog: use blocking assignment in combinatorial process
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2011-12-13 14:09:12 +01:00 |
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Sebastien Bourdeauducq
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a72faaecdd
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fhdl: allow a namespace to be specified for Verilog conversion
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2011-12-13 00:24:40 +01:00 |
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Sebastien Bourdeauducq
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eee6980a36
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fhdl: support Constant parameters for Verilog conversion
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2011-12-11 20:17:51 +01:00 |
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Sebastien Bourdeauducq
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dafef5d744
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fhdl: fix list references (thanks Lars)
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2011-12-11 20:17:29 +01:00 |
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Sebastien Bourdeauducq
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019ef16db4
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fhdl: remove broken fragment iadd
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2011-12-11 01:10:59 +01:00 |
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Sebastien Bourdeauducq
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b00581616e
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convtools: insert reset on variables
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2011-12-11 01:10:37 +01:00 |
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Sebastien Bourdeauducq
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d3127fd5d8
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autofragment: remove debug
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2011-12-10 20:48:23 +01:00 |
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Sebastien Bourdeauducq
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44f44b8a05
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fhdl: autofragment
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2011-12-10 20:47:21 +01:00 |
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Sebastien Bourdeauducq
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4b15a84505
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fhdl: fix += for empty fragment
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2011-12-10 20:47:06 +01:00 |
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Sebastien Bourdeauducq
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a49ecc4331
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fhdl: pad support in fragments
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2011-12-10 20:25:24 +01:00 |
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Sebastien Bourdeauducq
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fa63cc1ec8
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fhdl: replication support
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2011-12-09 13:11:34 +01:00 |
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Sebastien Bourdeauducq
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b0c5b74c22
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verilog: handle default in case statements
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2011-12-08 23:04:20 +01:00 |
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Sebastien Bourdeauducq
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512655c108
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fhdl: improve automatic signal naming
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2011-12-08 21:28:20 +01:00 |
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Sebastien Bourdeauducq
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84eb964adc
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fhdl: support negation operator
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2011-12-08 21:15:44 +01:00 |
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Sebastien Bourdeauducq
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bf021efa2b
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verilog: fix unary operator conversion
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2011-12-08 21:15:24 +01:00 |
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Sebastien Bourdeauducq
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ed05ec5f6a
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instances: signal override
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2011-12-08 18:56:14 +01:00 |
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Sebastien Bourdeauducq
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a6b86168ce
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Simple bus base class
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2011-12-08 18:47:32 +01:00 |
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Sebastien Bourdeauducq
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1b637cea61
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Instance support
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2011-12-08 16:35:32 +01:00 |
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Sebastien Bourdeauducq
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fab02f84cb
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fhdl: fix implicit slice index
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2011-12-07 22:21:30 +01:00 |
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Sebastien Bourdeauducq
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82f77180d5
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fhdl: cleanup value bv
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2011-12-07 22:21:10 +01:00 |
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Sebastien Bourdeauducq
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0e8d894a35
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Variable conversion
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2011-12-05 22:00:06 +01:00 |
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Sebastien Bourdeauducq
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4340680704
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Cleanup
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2011-12-05 19:25:32 +01:00 |
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Sebastien Bourdeauducq
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ec51f09c98
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Case support + register bank generator
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2011-12-05 17:43:56 +01:00 |
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Sebastien Bourdeauducq
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e099f4d52f
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Reset insertion
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2011-12-04 22:41:50 +01:00 |
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Sebastien Bourdeauducq
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cd8544c758
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Verilog generator
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2011-12-04 22:26:32 +01:00 |
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Sebastien Bourdeauducq
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499b95a519
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Initial import, FHDL basic structure, divider example
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2011-12-04 16:44:38 +01:00 |