Commit Graph

114 Commits

Author SHA1 Message Date
Sebastien Bourdeauducq 92f24b784d wishbone: decoder: fix slave cyc generation in registered mode 2011-12-13 14:08:39 +01:00
Sebastien Bourdeauducq 0ea7a9b2e6 wishbone2csr: fix double-write bug 2011-12-13 00:25:46 +01:00
Sebastien Bourdeauducq 923fc52e68 wishbone: only send ack to the active master in arbiter 2011-12-13 00:25:25 +01:00
Sebastien Bourdeauducq 16a6029a1b bus: fix CSR interconnect data readback 2011-12-11 20:17:12 +01:00
Sebastien Bourdeauducq dad9120653 bus: 14-bit CSR addresses 2011-12-11 20:16:50 +01:00
Sebastien Bourdeauducq 05d91c7104 bus: Wishbone to CSR bridge 2011-12-11 15:04:34 +01:00
Sebastien Bourdeauducq 4d1a960308 wishbone: decoder + shared bus interconnect 2011-12-09 13:11:52 +01:00
Sebastien Bourdeauducq 5c7131dc86 wishbone: arbiter 2011-12-08 23:21:25 +01:00
Sebastien Bourdeauducq c1041b9a5f simplebus: export GetSigName function 2011-12-08 23:06:04 +01:00
Sebastien Bourdeauducq 7c99e51b90 Named buses 2011-12-08 19:16:08 +01:00
Sebastien Bourdeauducq 5720a51dad wishbone: add missing SEL 2011-12-08 19:09:32 +01:00
Sebastien Bourdeauducq c43f3da534 Wishbone declarations 2011-12-08 18:47:41 +01:00
Sebastien Bourdeauducq a6b86168ce Simple bus base class 2011-12-08 18:47:32 +01:00
Sebastien Bourdeauducq 458cfc8623 CSR bus definitions 2011-12-05 00:16:44 +01:00