Commit Graph

8155 Commits

Author SHA1 Message Date
Florent Kermarrec 4b320a6a45 build/osfpga: Fix and switch to Raptor toolchain/Gemini device. 2022-07-04 18:52:47 +02:00
Florent Kermarrec 19d20786e3 build/efinix/xilinx: Fix. 2022-07-04 18:52:25 +02:00
enjoy-digital 4a23261499
Merge pull request #1356 from enjoy-digital/generic_toolchain
Introduce GenericToolchain and switch to it for build backends.
2022-07-04 18:35:44 +02:00
Florent Kermarrec dc6b81a13f Merge branch 'master' into generic_toolchain 2022-07-04 18:35:26 +02:00
Florent Kermarrec 08d1c53b80 build/xilinx/ise: Apply #1346. 2022-07-04 18:27:46 +02:00
Gwenhael Goavec-Merou eb0f00f295 build/generic_toolchain: _build -> build. All toolchains: override build only when required 2022-07-03 22:12:43 +02:00
Florent Kermarrec 1f1d9f5c0e cpu/neorv32: Initial switch to neorv32_litex_core_complex.
Status:
- Minimal/Lite variants working; Standard/Full are not (Related to cache?).
- GHDL does not seems to be able to convert VHDL to Verilog and keep parametrization;
we'll have to implement a workaround to be able to select variant and enable debug.
2022-06-29 15:48:07 +02:00
enjoy-digital 8eae77a310
Merge pull request #1347 from enjoy-digital/ci-cpus
test/test_cpu: Re-enable cv32e40p/marocchino.
2022-06-29 11:52:27 +02:00
Florent Kermarrec 7388684232 integration/export/get_memory_x: Replace spi_flash with rom.
Even when ROM is stored in SPI Flash, ROM regions has to be created.
2022-06-29 11:19:52 +02:00
Florent Kermarrec 9c3663f3d2 test/test_cpu: Re-enable cv32e40p/marocchino. 2022-06-29 11:15:48 +02:00
Florent Kermarrec b6d00238cb build/efinix/efinity/run_script: platform -> self.platform. 2022-06-29 10:33:00 +02:00
Florent Kermarrec 7af59fe1f7 build/xilinx/vivado: synth_mode -> self._synth_mode. 2022-06-29 10:18:14 +02:00
enjoy-digital bc6ce4b04b
Merge pull request #1346 from cklarhorst/master
build/xilinx/ise: Fix yosys flow
2022-06-29 10:16:06 +02:00
Gwenhael Goavec-Merou 382ebbf661 build: efinix/efinity lattice/diamond osfpga xilinx/f4pga xilinx/ise xilinx/yosys_nextpnr -> GenericToolchain 2022-06-28 22:21:24 +02:00
Gwenhael Goavec-Merou a4bb65655c build/generic_toolchain: store fragment. Reorder build_io_constraints and build_timing_constraints 2022-06-28 22:20:22 +02:00
Christian Klarhorst aec8cd5339 build/xilinx/ise: Fix yosys flow
The top name changed in 2016 but only XST was changed.
2022-06-28 15:26:14 +02:00
enjoy-digital ec9d1c4fd0
CI: Disable more CPUs. 2022-06-27 22:43:01 +02:00
Florent Kermarrec f898423390 test/test_cpu: Diable mor1kx/picorv32 for now due to issue with newer Verilator. 2022-06-27 19:54:50 +02:00
Florent Kermarrec 60d0c4ddd4 ci: Compile/Install Verilator from sources (Required for updated Vexriscv-SMP). 2022-06-27 18:53:02 +02:00
Florent Kermarrec 4ff839900b bios/cmd_litedram: Enable sdram_init/mr_write commands also for SDRAM. 2022-06-27 17:49:39 +02:00
Florent Kermarrec c4e3962def soc/add_etherbone: Expose IP Broadcast capability. 2022-06-27 15:46:57 +02:00
Gwenhael Goavec-Merou 6541a6c93b build: gowin lattice/diamond lattice/oxide lattice/radiant microsemi quicklogic move to GenericToolchain 2022-06-26 21:40:56 +02:00
Gwenhael Goavec-Merou 1f9bf1bd06 build/generic_toolchain: build_dir, vns now members. Adds build_placement_constraints call. Write verilog ASAP 2022-06-26 21:39:29 +02:00
Gwenhael Goavec-Merou 564c062074 build/xilinx/vivado: use GenericToolchain 2022-06-26 09:06:20 +02:00
Gwenhael Goavec-Merou 8446c5b342 build/anlogic: use GenericToolchain 2022-06-26 09:05:58 +02:00
Gwenhael Goavec-Merou b75a6ba636 build/lattice/icestorm: move parse_device and pnr_opts to finalize method 2022-06-26 09:05:22 +02:00
Gwenhael Goavec-Merou 418d0f3c0d build/generic_toolchain: finalize() method: for toolchain specifics tasks one platform ready 2022-06-26 09:04:00 +02:00
Gwenhael Goavec-Merou 83f3c42b89 build/sim/verilator: add (unused) backend parameter 2022-06-25 18:15:48 +02:00
Gwenhael Goavec-Merou 4a3c19cedc build/lattice/icestorm: add edalize as alternate backend 2022-06-25 17:10:23 +02:00
Gwenhael Goavec-Merou 04617027f4 build/lattice/icestorm: refactor the build options string for yosys and NextPnr 2022-06-25 15:36:38 +02:00
Gwenhael Goavec-Merou c8b336957f build/generic_toolchain, soc/integration/builder: introducing a backend argument and edalize as alternate backend 2022-06-25 15:22:30 +02:00
Gwenhael Goavec-Merou d1e610c400 build/{generic_toolchain, lattice/icestorm, lattice/trellis}: remove toolchain dependants parameters for build_io_constraints, build_timing_constraints, build_placement_constraints. Those must be intercepted at the level of the specific toolchain. 2022-06-24 21:11:31 +02:00
Florent Kermarrec 7117de0f1f build/lattice/icestorm/trellis: Generate Yosys script in build_project. 2022-06-24 10:33:51 +02:00
Florent Kermarrec 4c978bf463 build/generic_toolchain: Add add_false_path_constraint and remove it from altera/quartus, lattice/trellis. 2022-06-24 10:24:01 +02:00
Florent Kermarrec 6b59eb5cfe build/generic_toolchain/add_period_constraint: Integrated rounding to lowest picosecond and remove add_period_constraint from altera/quartus. 2022-06-24 10:19:59 +02:00
Florent Kermarrec 08a3b0ae4a build/generic_toolchain: Add build_placement_constraints method and switch other methods to *args, **kwargs for now. 2022-06-24 10:17:02 +02:00
Florent Kermarrec 1ecb9cec0a build/generic_toolchain: Rename constraints methods to build_io_constraints/build_timing_constraints. 2022-06-24 10:12:36 +02:00
Florent Kermarrec 08cc384a0c build/generic_toolchain: Fix build/copyrights and do minor cosmetic changes. 2022-06-24 09:51:46 +02:00
Gwenhael Goavec-Merou 9db1d9e49f toolchain: implement generic toolchain and devices toolchain refactoring 2022-06-24 09:20:42 +02:00
Rouven Broszeit fa234e8ed8 Do not call spisdcard_select for CMD0. 2022-06-23 16:17:05 +02:00
enjoy-digital e4c81e8fdf
Merge pull request #1338 from p-woj/litesdcard-init
software/liblitesdcard: Fix condition in sdcard_init
2022-06-22 19:42:23 +02:00
Florent Kermarrec ee1af96ab7 CHANGES: Update. 2022-06-22 18:13:49 +02:00
Piotr Wojnarowski e141826fd8 software/liblitesdcard: Fix condition in sdcard_init
Instead of retrying `sdcard_app_send_op_cond` until it returns an error,
retry until it completes successfully and the command response has the
busy bit set.
2022-06-22 14:44:28 +02:00
Florent Kermarrec 1a90549fa3 interconnect/axi/axi_full: Switch to our own AXI Interconnect (Shared & Crossbar).
We were not able to simulate verilog_axi interconnect/crossbar correctly since to what
seems to be a simulation mismatch. The code also seems to requires fixing some synthesis
issues with Yosys. When tested with Vivado, the SoC was also miss-behaving (not booting
correctly).

The simulation mismatch issue is logged here: https://github.com/enjoy-digital/litex_verilog_axi_test/issues/1

Since we already had our own AXI-Lite interconnect, creating our AXI interconnect can be
largely based on it with only minor modifications, so switch to it. This also allow simplification
in the interconnect selection/instance.
2022-06-20 19:51:31 +02:00
Florent Kermarrec 573479b395 interconnect:axi/axi_lite/interconnect: Cosmetic cleanups. 2022-06-20 19:13:44 +02:00
Florent Kermarrec bb1702e6d5 integration/export: Align MEM_REGIONS for BIOS display with mem_list.
Before:
litex> mem_list
Available memory regions:
ROM       0x00000000 0x10000
SRAM      0x01000000 0x2000
AXI_RAM   0x00010000 0x1000
AXI_DP_RAM_A  0x00011000 0x1000
AXI_DP_RAM_B  0x00012000 0x1000
AXI_RAM_REG  0x00013000 0x1000
AXI_RAM_FIFO  0x00014000 0x1000
AXI_RAM_XBAR  0x00100000 0x10000
AXI_RAM_INT  0x00200000 0x10000
CSR       0x82000000 0x10000

After:
litex> mem_list
Available memory regions:
ROM           0x00000000 0x10000
SRAM          0x10000000 0x2000
AXI_RAM       0x00010000 0x1000
AXI_DP_RAM_A  0x00011000 0x1000
AXI_DP_RAM_B  0x00012000 0x1000
AXI_RAM_REG   0x00013000 0x1000
AXI_RAM_FIFO  0x00014000 0x1000
AXI_RAM_XBAR  0x00100000 0x10000
AXI_RAM_INT   0x00200000 0x10000
CSR           0xf0000000 0x10000
2022-06-20 15:21:16 +02:00
enjoy-digital b00d22f56a
Merge pull request #1334 from antmicro/move_to_f4pga
Move from deprecated Symbiflow to F4PGA
2022-06-20 11:56:42 +02:00
enjoy-digital b8ee713dba
Merge pull request #1331 from cr1901/gowin-win
Gowin: Fix `copyfile` paths
2022-06-20 11:32:47 +02:00
Florent Kermarrec b66bd171cc litex_setup: Use recursive clone for litex_verilog_axi. 2022-06-20 11:23:00 +02:00
Florent Kermarrec 32d1589fb8 litex_setup: Move valentyusb to Misc Cores and also install litex_verilog_axi. 2022-06-20 11:01:47 +02:00