f1714405c3
integration/export: do not include soc.h in csr.h when with_access_functions=False
...
Idealy we should have another parameter for that.
2019-11-07 09:02:31 +01:00
b52dcde9ba
soc_sdram/kcu105: add optional main_ram_size_limit and use it on KCU105 to limit to 1GB instead of 2GB.
...
CSR map will need to be updated to support the 2GB.
2019-11-07 09:00:54 +01:00
9053d0803a
soc_sdram: remove use_full_memory_we parameter (always used as True)
2019-11-07 08:56:52 +01:00
1b94699d12
soc_sdram: update copyrights
2019-11-07 08:44:34 +01:00
2da421f64e
Merge pull request #300 from gsomlo/gls-rocket-axi
...
RFC: Direct link between Rocket/mem_axi <--> LiteDRAM dataport
2019-11-07 08:40:30 +01:00
28708f4208
cpu/rocket: parameterize axi interface data width
...
Rocket variants can be configured with axi port data widths that
are multiples of the native word size (64 bits in our case). In
the future, we will add variants with mem_axi data width > 64 bit,
to match the native data width of the LiteDRAM controller on
various development boards (e.g., 128 bits on the ecp5versa, and
256 bits on the trellisboard).
Signed-off-by: Gabriel Somlo <gsomlo@gmail.com>
2019-11-01 08:55:27 -04:00
014db66444
soc_sdram: remove upper limit on usable main RAM
...
Revert commit #68a503174.
2019-11-01 08:55:15 -04:00
ec831f5b63
cpu/rocket, soc_sdram: Connect mem_axi to LiteDRAM, bypass WB bus
...
Connect Rocket's dedicated port for cached RAM accesses (mem_axi)
directly to the LiteDRAM data port, bypassing the shared LiteX
(Wishbone) bus.
When both Rocket's mem_axi and LiteDRAM's port have the same data
width, use a native point-to-point AXI connection.
Otherwise, convert both ends to Wishbone, and use the Wishbone
data width converter to bridge the gap.
FIXME: In the future, this part should be replaced with a native
AXI data width converter!
Signed-off-by: Gabriel Somlo <gsomlo@gmail.com>
2019-11-01 08:52:39 -04:00
9c3c43c94a
interconnect/csr_bus/SRAM: add mem_size check
...
Memory size is limited to 512 bytes:
- CSR region size is 0x800 (4096)
- default csr_data_width is 8
maximum size = 4096/8 = 512 bytes.
2019-11-01 11:33:50 +01:00
edb1731ef9
soc_core/soc_core_args: specify default cpu (vexriscv)
2019-11-01 11:30:50 +01:00
cc607f022a
lattice/diamond/tcl: always use / separators, even on windows
2019-11-01 10:11:12 +01:00
59acf0ea1c
cpu/minerva: elaborate minerva verilog to build directory
2019-11-01 09:59:13 +01:00
a762d29b19
soc/integration/builder: pass output_dir to platform, make sure gateware/software directory are created before finalizing
2019-11-01 09:59:06 +01:00
855d0e925d
cpu/minerva: generate minerva.v near core.py not in submodule
2019-10-31 21:16:27 +01:00
85d6607257
cpu/minverva: give more explicit error message when not able to elaborate cpu
2019-10-31 08:52:04 +01:00
3465fc96d4
Merge pull request #297 from mithro/mem-region-pp
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Improve the error message on memory region conflict.
2019-10-30 20:49:27 -07:00
4408dad9d2
Improve the error message on memory region conflict.
...
Before;
```
ValueError: Memory region conflict between rom and main_ram
```
After;
```
ValueError: Memory region conflict between rom (<SoCMemRegion 0x10000000 0x10000 cached>) and main_ram (<SoCMemRegion 0x0 0x20000000 cached>)
```
Fixes #296 .
2019-10-30 19:32:20 -07:00
bb64f8a74d
Merge pull request #293 from mithro/mor1kx-fix
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Fix file names for the mor1kx processor.
2019-10-30 14:28:48 -07:00
607e1cc4f6
Fix file names for the mor1kx processor.
...
Fixes #292 .
2019-10-30 13:50:01 -07:00
a54b80b9b4
targets: use type="io" instead of io_region=True
2019-10-30 16:42:31 +01:00
a0c0a6fd05
integration/SoCMemRegion: use type instead of io_region/linker_region and export type to csv/json
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Supported types: "cached", "io", "cached+linker", "io+linker", default="cached"
2019-10-30 16:42:26 +01:00
9fcf297387
soc_core: add check_regions_overlap method, add linker_region support (overlap is not checked on linker_regions)
2019-10-28 18:34:03 +01:00
4014fbffe1
soc_core/add_memory_region: fix memory overlap detection
2019-10-28 17:07:37 +01:00
650df0ebc2
test/test_targets: skip Minerva test on Travis-CI, remove commented tests
2019-10-28 11:00:08 +01:00
ab8af28213
cpu/minerva: elaborate from nmigen sources during build, enable hardware multiplier
2019-10-28 10:23:08 +01:00
4cc40aadaa
Merge pull request #286 from gsomlo/gls-timingstrict
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build/lattice/trellis: optionally allow failure if p&r timing not met
2019-10-25 12:28:29 +02:00
49372852da
build/lattice/trellis: optionally allow failure if p&r timing not met
...
When timing requirements are strict, allow the build process to fail upon
failure to meet timing. This facilitates running the build process from a
loop, repeatedly, until a "lucky" p&r solution is found, e.g.:
while true; do
litex/boards/targets/versa_ecp5.py --gateware-toolchain trellis \
--sys-clk-freq=60e06 --cpu-type rocket --cpu-variant linux \
--with-ethernet --yosys-nowidelut \
--nextpnr-timingstrict
if [ "$?" == "0" ]; then
echo "Success" | mail -s "Build Succeeded" your@email.here
break
fi
done
This augments commit #683e0668, which unconditionally forced p&r to
succeed, regardless of whether timing was met, via '--timing-allow-fail'.
Signed-off-by: Gabriel Somlo <gsomlo@gmail.com>
2019-10-24 13:56:20 -04:00
b6d35c92ae
Merge pull request #283 from kbeckmann/kbeckmann/bios_increment_address
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bios: Increment address when writing to flash
2019-10-20 15:30:22 +02:00
ef78ae951f
bios: Increment address when writing to flash
2019-10-19 22:58:24 +02:00
683e066812
build/lattice/trellis: use --timing-allow-fail to allow generating bistream when timings are not met
...
This is the default behaviour of the others tools and allow testing designs on hardware with small violations.
2019-10-18 14:12:01 +02:00
4cf346a1d4
soc/cores/icap/ICAPBitstream: always keep fifo.source.ready to 1
2019-10-18 10:27:37 +02:00
39862f068e
Merge pull request #282 from antmicro/icapbitstream_fixes
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Fix ICAPBitstream
2019-10-18 10:24:20 +02:00
8b5da9c623
cores/icap/ICAPBitstream: add source ready signal.
2019-10-18 09:33:31 +02:00
626533ce9d
soc/integration/__init__: remove imports (not used and causing issues
2019-10-17 12:44:37 +02:00
675b455259
build: always use platform.add_source and avoid manipulate platform.sources directly
2019-10-17 12:17:36 +02:00
43f5d1ef13
build/generic_platform: replace set with list for sources/verilog_include_paths
...
Python does not have native OrderedSet and we need to be able to preserve the order of the sources
for some backends (Verilator for instance), so use list instead of set.
2019-10-17 09:52:49 +02:00
97a77b950c
cores/icap/ICAPBitstream: simplify, add icap_clk_div parameter, describe how to use it.
2019-10-16 15:00:58 +02:00
98c224be15
build/generic_platform: keep language to None if None after tools.language_by_filename
2019-10-15 12:14:37 +02:00
14dae8bd73
soc_core: fix default --uart_name
2019-10-14 22:15:02 +02:00
ba26441889
integration/soc_core: expose more SoC parameters
2019-10-14 09:12:25 +02:00
23d8396144
Merge pull request #280 from kbeckmann/picorv32_typo
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picorv32: Fix minimal variant params
2019-10-13 11:29:46 -07:00
0e467168fd
picorv32: Fix minimal variant params
...
The param p_ENABLE_COUNTERS was misspelled.
2019-10-13 12:56:55 +02:00
ef504f62af
soc_core: fix soc_core_argdict
2019-10-12 23:05:53 +02:00
cd8213b988
cpu/lm32: add missing buses
2019-10-12 19:20:50 +02:00
5a0358754d
soc_core/soc_core_argdict: use inspect to get all parameters and simplify
2019-10-12 19:18:57 +02:00
96c369f3e4
integration: simplify cpu buses auto-conversion (always use Converter, thanks gsomlo)
2019-10-11 21:55:26 +02:00
29e51f5e97
interconnect/wishbone: fix Converter case when buses are identical
2019-10-11 21:49:11 +02:00
ae9c25b74f
platforms/versa_ecp5: add serdes refclk/sma
2019-10-11 19:51:38 +02:00
9a82933858
cpu/rocket: expose 64-bit buses (use automatic down-conversion of SoCCore)
2019-10-11 09:01:50 +02:00
ca81cc209b
soc_core: add automatic down-conversion of CPU buses to 32-bit (if needed)
2019-10-11 09:01:08 +02:00
Florent Kermarrec
Gabriel Somlo
Tim Ansell
Konrad Beckmann
Jan Kowalewski