Commit Graph

5703 Commits

Author SHA1 Message Date
enjoy-digital 177c1e5397
Merge pull request #523 from DurandA/patch-5
Update litex_term help
2020-05-14 07:17:46 +02:00
Arnaud Durand 9d9e7d54cd
Update litex_term help
Specify the use of kernel address with flash flag.
2020-05-13 22:50:09 +02:00
Florent Kermarrec 2e59dc329d platforms/nexys4ddr: add card detect pin to sdcard. 2020-05-13 19:11:46 +02:00
Florent Kermarrec 51742be2bb integration/soc: review/simplify interconnect and add logger.info. 2020-05-13 18:29:12 +02:00
enjoy-digital 78413cc09e
Merge pull request #519 from ozbenh/point2point
soc: Revive generation of a PointToPoint interconnect
2020-05-13 16:48:21 +02:00
Benjamin Herrenschmidt 1ed6869110 soc: Revive generation of a PointToPoint interconnect
When there's only one master, one slave, and that slave is at 0

Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
2020-05-14 00:06:53 +10:00
Florent Kermarrec 748ef1add3 export: add define of CSR_BASE if not already defined and use it for CSRs definitions/accesses.
This will allow more flexibility when integrating standalone cores.
2020-05-13 15:56:20 +02:00
Florent Kermarrec 9f941138d2 test/test_targets: workaround to fix travis. 2020-05-13 11:04:40 +02:00
Florent Kermarrec 9d1443c1a8 cpu/soc_core: automatically set csr mapping to 0x00000000 when using CPUNone, remove csr_base parameter that was used for that. 2020-05-13 09:31:20 +02:00
Florent Kermarrec 5ea3bae036 bios/boot: review/fix #503.
- copy_image_from_flash_to_ram is now used by all CPUs.
- copy_image_from_flash_to_ram already show the flash address, no need to duplicate it.
2020-05-13 08:44:17 +02:00
enjoy-digital bf7857f553
Merge pull request #503 from rprinz08/master
BIOS boot firmware from SPI with address offset
2020-05-13 08:36:43 +02:00
enjoy-digital b4e349eb49
Merge pull request #513 from mubes/bios_linker
Bios linker edits to prevent inappropriate optimisation
2020-05-13 07:52:37 +02:00
Dave Marples d2d82dacf2 Bios linker edits to prevent inappropriate optimisation 2020-05-12 23:32:49 +01:00
rprinz08 1f55fcf449 fixed bug in BIOS spi flash "fw" command 2020-05-12 16:58:42 +02:00
rprinz08 f062c0c44b removed FLASH_BOOT_OFFSET, replaced memcyp with copy_image_from_flash_to_ram 2020-05-12 16:57:21 +02:00
Florent Kermarrec 3fb99b7d33 cores/spi_flash: add back old SpiFlashDualQuad and rename new one as SpiFlashQuadReadWrite. 2020-05-12 16:51:47 +02:00
enjoy-digital 2a5a7536b8
Merge pull request #478 from antmicro/extended_spi_flash
Extended SPI flash support
2020-05-12 16:42:01 +02:00
enjoy-digital 7d79da8eda
Merge pull request #510 from mubes/colorlight_usb
Colorlight usb
2020-05-12 16:35:29 +02:00
Florent Kermarrec 3a6dd95d6f integration/soc: review/simplify changes for standalone cores.
- do the CSR alignment update only if CPU is not CPUNone.
- revert PointToPoint interconnect when 1 master and 1 slave since this will
break others use cases and will prevent mapping slave to a specific location.
It's probably better to let the synthesis tools optimize the 1:1 mapping directly.
- add with_soc_interconnect parameter to add_sdram that defaults to True. When
set to False, only the LiteDRAMCore will be instantiated and interconnect with
the SoC will not be added.
2020-05-12 16:18:26 +02:00
Dave Marples 8499733289 Fix dumb missing line 2020-05-12 14:40:11 +01:00
enjoy-digital 0d5eb13359
Merge pull request #511 from ozbenh/standalone-cores
Improve standalone cores
2020-05-12 14:55:44 +02:00
Florent Kermarrec 873d95e517 interconnect/wishbonebridge: refresh/simplify.
This should also improve Wishbone timings.

Tested on iCEBreaker:
./icebreaker.py --cpu-type=None --uart-name=uartbone --csr-csv=csr.csv --build --flash

With the following script:

#!/usr/bin/env python3

import sys

from litex import RemoteClient

wb = RemoteClient()
wb.open()

# # #

print("scratch: 0x{:08x}".format(wb.regs.ctrl_scratch.read()))

errors = 0
for i in range(2):
for j in range(32):
wb.write(wb.mems.sram.base + 4*j, i + j)
for j in range(32):
if wb.read(wb.mems.sram.base + 4*j) != (i + j):
errors += 1
print("sram errors: {:d}".format(errors))

# # #

wb.close()
2020-05-12 13:40:28 +02:00
Benjamin Herrenschmidt f628ff6b47 WB2CSR: Use CSR address_width for the wishbone bus
Currently, we create a wishbone interface with the default address
width (30 bits) for the bridge. Instead, create an interface that
has the same number of address bits as the CSR bus.

Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
2020-05-12 21:37:36 +10:00
Benjamin Herrenschmidt 520c17e96d soc_core: Add option to override CSR base
When creating standalone IP cores such as standalone LiteDRAM without
a CPU, the CSR are presented externally via a wishbone with just enough
address bits to access individual CSRs (14), and no address decoding
otherwise. It is expected that the design using such core will have
its own address decoder gating cyc/stb.

However, such a design might still need to use LiteX code such as
the sdram init code, which relies on the generated csr.h. Thus we
want to be able to control the CSR base address used by that generated
csr.h.

This could be handled instead by having the "host" code provide
modified csr_{read,write}_simple() that include the necessary base
address. However, such an approach would make things complicated
if the design includes multiple such standalone cores with separate
CSR busses (such as LiteDRAM and LiteEth).


Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
2020-05-12 21:35:12 +10:00
Benjamin Herrenschmidt ecbd40284a soc: Don't update CSR alignment when there is no CPU
The alignment specified by the standalone core config should
be honored.

Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
2020-05-12 21:31:23 +10:00
Benjamin Herrenschmidt f28f247130 soc: Don't create a wishbone slave to LiteDRAM with no CPU
When creating a standalone LiteDRAM core with no CPU, there is
no need to create a wishbone slave to LiteDRAM interface.

Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
2020-05-12 21:30:19 +10:00
Dave Marples 33e202edd4 Bring into line with master 2020-05-12 12:28:09 +01:00
Benjamin Herrenschmidt dcc881db92 soc: Don't create a share intercon with only one master and one slave
This creates a lot of useless churn in the resulting verilog. Instead
use a point to point interconnect in that case.

Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
2020-05-12 20:58:19 +10:00
enjoy-digital c136113a9b
Merge pull request #506 from scanakci/blackparrot_litex
Update README and core.py for Blackparrot and change vivado command for systemverilog
2020-05-12 11:41:25 +02:00
enjoy-digital d2c9d38567
Merge pull request #508 from antmicro/update_litesdcard
Update Litex bios to handle updated litesdcard.
2020-05-12 11:38:09 +02:00
Dave Marples dc1d452008 Addition of boot address parameter for trellis builds 2020-05-12 09:41:37 +01:00
Kamil Rakoczy 0db3506997 Update Litex bios to handle updated litesdcard. 2020-05-12 10:07:16 +02:00
sadullah aed1d514ab Update README.md and core.py for BlackParrot 2020-05-12 03:06:38 -04:00
sadullah 5e4a436089 Vivado Command Update for Systemverilog
Add BlackParrot to LiteX setup file
2020-05-12 03:05:41 -04:00
enjoy-digital 3ce9010083
Merge pull request #505 from DurandA/patch-3
Enable 1x mode on SPI flash
2020-05-11 22:53:31 +02:00
Florent Kermarrec e2176cefc2 soc: remove with_wishbone (a SoC always always has a Bus) and expose more bus parameters. 2020-05-11 22:39:17 +02:00
Arnaud Durand 2c40967b5a Enable 1x mode on SPI flash 2020-05-11 22:12:40 +02:00
Florent Kermarrec 1e610600f6 build/lattice/diamond/clock_constraints: review and improve similarities with the others build backends. 2020-05-11 10:52:39 +02:00
enjoy-digital ebcf67c10f
Merge pull request #502 from shuffle2/master
diamond: project generation improvements
2020-05-11 09:55:52 +02:00
enjoy-digital 80f5327e3d
Merge pull request #490 from daveshah1/rdimm_bside_init
Add RDIMM side-B inversion support
2020-05-11 09:42:55 +02:00
enjoy-digital 13db89ebd2
Merge branch 'master' into rdimm_bside_init 2020-05-11 09:42:35 +02:00
Florent Kermarrec c9e36d7fdd lattice/icestorm: add ignoreloops/seed support (similar to trellis) and icestorm_args. 2020-05-11 09:33:26 +02:00
Florent Kermarrec ea7fe383a3 lattice/trellis: simplify seed support and add it to trellis_args. 2020-05-11 09:26:12 +02:00
enjoy-digital 5ee01c9460
Merge pull request #484 from ilya-epifanov/lattice-trellis-toolchain-seed
Can now pass `--seed` to `nextpnr-ecp5` via `TrellisToolchain` `kwargs`
2020-05-11 09:13:26 +02:00
enjoy-digital 5987ddb454
Merge pull request #485 from ilya-epifanov/cpu-imac-config-for-vexriscv
Added `imac` config for CPUs …
2020-05-11 08:58:28 +02:00
enjoy-digital c5f74a5aa7
Merge branch 'master' into cpu-imac-config-for-vexriscv 2020-05-11 08:58:20 +02:00
Florent Kermarrec 59d88a880c integration/soc/add_adapter: rename is_master to direction. 2020-05-11 08:47:50 +02:00
enjoy-digital 57390666d8
Merge pull request #504 from sergachev/master
integration/soc: fix add_adapter for slaves
2020-05-11 08:34:03 +02:00
Ilia Sergachev e4fa4bbcf7 integration/soc: fix add_adapter for slaves 2020-05-10 11:32:34 +02:00
Benjamin Herrenschmidt 2d70220b80 bios: Fix warning on 64-bit
This fixes an incorrect printf format specifier

Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
2020-05-09 19:44:43 +02:00