5 Commits

Author	SHA1	Message	Date
Sebastien Bourdeauducq	d554a06eba	interconnect/wishbone: fix CSRBank init	2015-11-03 18:45:23 +08:00
Sebastien Bourdeauducq	2520ab480b	wishbone: add read/write simulation methods	2015-11-03 10:37:31 +08:00
Sebastien Bourdeauducq	67133f3542	replace flen with len	2015-09-26 18:50:11 +08:00
Sebastien Bourdeauducq	75ef2f9004	fix most imports	2015-09-25 18:43:20 +08:00
Sebastien Bourdeauducq	f69674e89c	interconnect: add bus/bank components from Migen	2015-09-24 20:48:18 +08:00