40740d3ddc
litepcie: use optional platform.misoc_path to add litepcie phy wrapper verilog files
...
We should eventually try to use python package_data or data_file for that.
2015-07-22 18:09:04 +02:00
a99aa9c7fd
uart: rename wishbone to bridge
2015-05-09 16:24:28 +02:00
fb5397aa82
uart: remove litescope dependency for UARTWishboneBridge and remove frontend
2015-05-09 16:08:20 +02:00
c98bd9fd79
rename shadow_address to shadow_base (more appropriate) and use | instead of + (as done in artiq)
2015-05-02 17:07:58 +02:00
3ebe877fd2
use similar names for wishbone bridges and move wishbone drivers to [core]/software
2015-05-02 16:22:30 +02:00
1281a463d6
litescope/bridge: create a generic wishbone bridge that can be used with different phys (the phy needs to provide a sink/source with 8bits data).
...
- we can now pass a phy to LiteScopeWishboneBridge
- LiteScopeUART2Wishbone is only a specific LiteScopeWishboneBridge
- UART mux is removed since complicated and no longer useful (we can now create easily virtual UART over Ethernet, USB or PCIe) or simply add another UART for debug.
2015-05-01 17:51:18 +02:00
d22d58c7cc
add litepcie core
2015-04-17 13:45:01 +02:00
Florent Kermarrec