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9109 Commits

Author SHA1 Message Date
Christian Klarhorst b010455415 integration/builder Make bios console configurable 2022-08-29 10:40:31 +02:00
enjoy-digital 50a5e137ff
Merge pull request #1405 from jrudolph/better-meson-error-msg 
soc/integration/builder: more precise error message when meson is too old
 2022-08-24 19:36:23 +02:00
Johannes Rudolph 64e5de9fc8
soc/integration/builder: more precise error message when meson is too old 2022-08-23 19:02:41 +02:00
Gabriel Somlo 01754a82c8 integration/soc: fix sata irq initialization 
The first argument to `self.irq.add()` should match the name of the
`EventManager()` object being added, i.e., "sata_irq" rather than
just plain "sata". This is necessary for interrupt signals to be
asserted as intended.

Signed-off-by: Gabriel Somlo <gsomlo@gmail.com>
 2022-08-19 14:37:22 -04:00
Dolu1990 78a1dbbc8b
Merge pull request #1402 from enjoy-digital/naxriscv-merge 
cpu/NaxRiscv fix LSU deadlock
 2022-08-18 17:32:16 +02:00
Dolu1990 89522f6980 cpu/NaxRiscv fix LSU deadlock 2022-08-18 10:36:19 +02:00
Tim 'mithro' Ansell 33ae301d0d
Merge pull request #1395 from lschuermann/dev/missing-cpus-manifest 
Add missing soc/cores/cpu directories to MANIFEST.in
 2022-08-10 09:57:53 -07:00
Leon Schuermann 727cc40ab1 Add missing soc/cores/cpu directories to MANIFEST.in 2022-08-09 20:30:04 +02:00
Dolu1990 552d7bdb5c cpu/NaxRiscv: update 2022-08-08 10:53:06 +02:00
Dolu1990 ec4c8741d4 cpu/NaxRiscv: update 2022-08-08 10:51:23 +02:00
enjoy-digital c4e635ea5c
Merge pull request #1393 from trabucayre/fix_vivado_yosys_synth 
build/xilinx/vivado: Insert the yosys call into script_content only when synth_mode == yosys
 2022-08-05 17:30:14 +02:00
Florent Kermarrec b792bfd8b2 tools/litex_client/run_gui: Add Identifier/Leds/Buttons peripherals support. 2022-08-05 15:25:13 +02:00
Gwenhael Goavec-Merou ae44b70833 build/xilinx/vivado: Insert the yosys call into script_content only when synth_mode == yosys 2022-08-05 14:51:39 +02:00
Florent Kermarrec 95a4814184 tools/litex_client: Improve run_gui termination. 2022-08-05 14:12:37 +02:00
Florent Kermarrec 68006a2144 tools/litex_client: Add XADC (7-Series) suppport to GUI. 2022-08-05 13:49:26 +02:00
Florent Kermarrec ae8deda186 interconnect/axi/AXIArbiter: valid also needs to be filtered. 
Fixes un-sollicited valids on masters.
 2022-08-05 11:20:52 +02:00
Florent Kermarrec a286d77e01 build/xilinx/vivado: Switch from .format to f-strings. 2022-08-05 08:59:32 +02:00
Florent Kermarrec 2fba07daf8 build/gowin: Use build_name instead of top for generated files. 2022-08-05 08:30:34 +02:00
Florent Kermarrec 3c1e8e74fc build: Cosmetic cleanups. 2022-08-05 08:22:36 +02:00
enjoy-digital c2b62a6b0c
Merge pull request #1392 from tpwrules/fix-vexriscsmp-quartus 
cores/cpu/vexriscv_smp: define SYNTHESIS in Quartus
 2022-08-05 08:02:29 +02:00
enjoy-digital 1f2d0e120b
Merge pull request #1391 from dlobato/fix-verilator-fst-trace 
build/sim/verilator: fixed missing placeholder
 2022-08-05 08:02:08 +02:00
Thomas Watson 195cc915ed cores/cpu/vexriscv_smp: define SYNTHESIS in Quartus 2022-08-04 21:34:56 -05:00
David Lobato 41e1ccce4b build/sim/verilator: fixed missing placeholder 2022-08-04 20:03:29 +01:00
Florent Kermarrec 926fb9a30a build/xilinx/vivado: Fix build. 2022-08-04 17:59:12 +02:00
Florent Kermarrec 47df2f6983 bios/cmd_bios: Add buttons command to get buttons value. 2022-08-04 16:31:12 +02:00
enjoy-digital 8250f56f80
Merge pull request #1389 from trabucayre/rfc_yosys_nextpnr_wrapper 
RFC: yosys nextpnr wrapper
 2022-08-04 15:02:35 +02:00
Dolu1990 1ce378e24d
Merge pull request #1390 from tpwrules/add-linux-vexriscv_smp 
cores/cpu/vexriscv_smp: add default cores used by linux with l2 cache
 2022-08-04 12:19:37 +02:00
Mateusz Hołenko 6932fc51e2
Merge pull request #1388 from p-woj/json2renode-fb-plic 
tools/litex_json2renode: Add video_framebuffer support, vexriscv interrupt fixes
 2022-08-02 15:35:06 +02:00
Thomas Watson 35e0de043d cores/cpu/vexriscv_smp: add default cores used by linux with l2 cache 2022-07-31 22:31:33 -05:00
Florent Kermarrec 7789e1875a build/gowin: Fix build regression (build_name -> self._build_name). 2022-07-26 09:59:20 +02:00
Gwenhael Goavec-Merou d5b0f9263d build: lattice/radiant.py xilinx/common.py xilinx/ise.py xilinx/vivado.py: use yosys_wrapper 2022-07-25 22:35:55 +02:00
Gwenhael Goavec-Merou 21105669a8 build: lattice/icestorm, lattice/oxide, lattice/trellis, xilinx/yosys_nextpnr: inherits from YosysNextPNRToolchain 2022-07-25 22:05:21 +02:00
Gwenhael Goavec-Merou 6d6076d8c6 build/yosys_nextpnr_toolchain: GenericToolchain subclass targeted for toolchains based on Yosys+nextPNR+packer tool suite 2022-07-25 22:00:26 +02:00
Gwenhael Goavec-Merou 32c750c12e build/nextpnr_wrapper: a NextPNR wrapper 2022-07-25 21:58:44 +02:00
Gwenhael Goavec-Merou b2adabbece build/yosys_wrapper: a Yosys wrapper 2022-07-25 21:58:18 +02:00
Piotr Wojnarowski 456822a5fa tools/litex_json2renode: Add video_framebuffer support 2022-07-25 13:38:12 +02:00
Piotr Wojnarowski c149f3e4dd tools/litex_json2renode: Add find_memory_region helper 2022-07-25 13:38:12 +02:00
Piotr Wojnarowski 98168492de tools/litex_json2renode: Save filtered memory regions for peripheral generators 2022-07-25 13:38:12 +02:00
Piotr Wojnarowski 124a2b2d56 tools/litex_json2renode: Don't disable built-in IRQ controller on vexriscv_smp 
The built-in IRQ controller is needed by linux-on-litex-vexriscv
 2022-07-25 13:37:25 +02:00
Piotr Wojnarowski dae22a0d9d tools/litex_json2renode: Update PLIC interrupt configuration 2022-07-25 13:30:09 +02:00
Piotr Wojnarowski 212db12b1d tools/litex_json2renode: Skip braces on MappedMemory registration 2022-07-25 13:25:17 +02:00
Piotr Wojnarowski 4f471490a8 tools/litex_json2renode: Output silenced range start address as hex 2022-07-25 13:25:17 +02:00
Florent Kermarrec 74467e3b38 test/test_axi/test_axi_width_converter: Switch to DUT_ref (To avoid breaking CI). 
We'll switch back to DUT when AXI Converter will be fixed.
 2022-07-25 12:34:38 +02:00
enjoy-digital c734732ece
Merge pull request #1386 from sergachev/feature/test_axi_width_conversion 
test: add axi 64b to 32b conversion test
 2022-07-25 12:29:42 +02:00
enjoy-digital f691aecb95
Merge pull request #1387 from sergachev/fix/cva6 
cpu/cva6: add optional peripheral bus conversion +
 2022-07-25 12:22:29 +02:00
enjoy-digital 8de83550a1
Merge pull request #1385 from sergachev/fix/verilator_includes 
sim: enable relative include paths for verilator
 2022-07-25 12:11:04 +02:00
enjoy-digital 29c2aed64a
Merge pull request #1384 from trabucayre/fix_xilinx_yosys_nextpnr_toolchain 
build/xilinx/yosys_nextpnr: _run_make -> run_script
 2022-07-25 12:10:41 +02:00
Ilia Sergachev 982f94ba8d test: add axi 64b to 32b conversion test 2022-07-25 00:20:48 +02:00
Ilia Sergachev 20affcfc31 cpu/cva6: add optional peripheral bus conversion to bypass axi width conversion problem; fix add_jtag; cleanup 2022-07-24 23:41:49 +02:00
Ilia Sergachev 7613c90fcd sim: enable relative include paths for verilator 2022-07-24 23:02:41 +02:00