Hardware
/
litex
mirror of https://github.com/enjoy-digital/litex.git
1
0
Fork 0
Code Issues Packages Projects Releases Wiki Activity
339 Commits 40 Branches 14 Tags 51 MiB
Commit Graph

51 Commits

Author SHA1 Message Date
Sebastien Bourdeauducq 4dcec32010 top: allocate one more ASMI port to framebuffer 2013-03-28 20:46:00 +01:00
Sebastien Bourdeauducq 8fd092ca12 crg: support VGA pixel clock reprogramming 2013-03-28 19:07:17 +01:00
Sebastien Bourdeauducq 1e860c7472 Use new Mibuild generic_platform API 2013-03-26 17:57:17 +01:00
Sebastien Bourdeauducq fdf7f10f54 Automatically build CSR access functions 2013-03-25 14:42:48 +01:00
Sebastien Bourdeauducq eaef3464e9 Instantiate DVI sampler core for both ports 2013-03-13 19:56:56 +01:00
Sebastien Bourdeauducq a9b723568a Use new module, autoreg and eventmanager Migen APIs 2013-03-10 19:32:38 +01:00
Sebastien Bourdeauducq 5649e88a90 Use Mibuild 2013-02-11 18:23:06 +01:00
Sebastien Bourdeauducq 0392dd8ac2 bank/csrgen: interface -> bus 2012-12-06 17:15:47 +01:00
Sebastien Bourdeauducq fee70e9866 Use Wishbone SRAM component from Migen 2012-12-01 12:59:32 +01:00
Sebastien Bourdeauducq 7e2bc00c0a Remove Constant 2012-11-28 23:18:53 +01:00
Sebastien Bourdeauducq c86dd3cbef Define clock domains instead of passing extra clocks as regular signals 2012-09-11 00:21:07 +02:00
Sebastien Bourdeauducq 5931c5eb59 Basic support for new clock domain and instance API 2012-09-10 23:47:06 +02:00
Sebastien Bourdeauducq 855eec776d Add ASMIprobe core 2012-08-04 16:31:24 +02:00
Sebastien Bourdeauducq 6073f68b69 asmicon: simple selector option 2012-07-13 19:25:38 +02:00
Sebastien Bourdeauducq b7aec21a47 top: use two slots for the framebuffer ASMI port 2012-07-12 19:40:49 +02:00
Sebastien Bourdeauducq a52c3135c1 framebuffer: frame initiator 2012-06-17 17:22:02 +02:00
Sebastien Bourdeauducq 3a02524cc7 VGA framebuffer connections 2012-06-17 13:41:26 +02:00
Sebastien Bourdeauducq f6f42293d1 Clock frequency detection 2012-05-22 13:23:44 +02:00
Sebastien Bourdeauducq c01594f9fd Common interrupt numbers 2012-05-21 19:52:41 +02:00
Sebastien Bourdeauducq 94245517f2 Add timer 2012-05-21 19:46:04 +02:00
Sebastien Bourdeauducq 8ad251c94c Connect Ethernet IRQ 2012-05-20 23:48:41 +02:00
Sebastien Bourdeauducq 4e18e45686 Add Ethernet MAC 2012-05-20 00:30:03 +02:00
Sebastien Bourdeauducq 79124d822b Identifier 2012-05-17 01:41:41 +02:00
Sebastien Bourdeauducq 141269b384 Get CSR base addresses from include file 2012-05-16 10:36:46 +02:00
Sebastien Bourdeauducq 19b1cc2529 Remove uses of pads, new constraints system 2012-04-02 19:22:17 +02:00
Sebastien Bourdeauducq c26efa28ca asmicon: multiplexer (untested) 2012-03-18 22:11:01 +01:00
Sebastien Bourdeauducq 0e00837f42 asmicon: move slot time to timing settings 2012-03-18 14:57:31 +01:00
Sebastien Bourdeauducq b1eb919ad2 asmicon: bank machine (untested) 2012-03-18 00:12:03 +01:00
Sebastien Bourdeauducq 7c377880fa asmicon: refresher (untested) 2012-03-15 20:29:26 +01:00
Sebastien Bourdeauducq 7b14e0bd05 asmicon: skeleton 2012-03-14 18:26:05 +01:00
Sebastien Bourdeauducq b4e041ecf1 s6ddrphy: write path OK in simulation 2012-02-20 23:55:20 +01:00
Sebastien Bourdeauducq f35cd4a85b Prepare for new DDR PHY 2012-02-19 18:43:42 +01:00
Sebastien Bourdeauducq 026457a98c Send SDRAM initialization sequence and answer PHY read/write requests. Obstinately refuses to work, unfortunately. 2012-02-18 18:12:14 +01:00
Sebastien Bourdeauducq 5bc840b9c1 DFI injector (untested) 2012-02-17 23:50:10 +01:00
Sebastien Bourdeauducq c387ce7ce5 Map DDR PHY controls in CSR 2012-02-17 17:34:59 +01:00
Sebastien Bourdeauducq 5d1dad583b Connect DDR PHY 
Doesn't do much for the moment, just to check synthesis/P&R.
 2012-02-17 11:04:44 +01:00
Sebastien Bourdeauducq 72f9af9d90 Generate all clocks for the DDR PHY 2012-02-16 18:02:37 +01:00
Sebastien Bourdeauducq 5165ff7ec3 Include Wishbone to ASMI bridge 2012-02-13 23:12:57 +01:00
Sebastien Bourdeauducq 58f4f78d2c sram: fix sub-word write 2012-02-06 23:13:35 +01:00
Sebastien Bourdeauducq 33f1c456bf top: connect UART IRQ 2012-02-06 17:45:40 +01:00
Sebastien Bourdeauducq 9b9a510525 Memory map 2012-02-05 19:54:08 +01:00
Sebastien Bourdeauducq 28f00c3a9a Add on-chip SRAM 2012-01-27 22:09:03 +01:00
Sebastien Bourdeauducq 6fde54c5aa Use meaningful class names 2012-01-21 12:25:22 +01:00
Sebastien Bourdeauducq f6aa95a4d0 Use new verilog.convert API 2012-01-20 23:00:11 +01:00
Sebastien Bourdeauducq 570ea8ccf8 convtools -> tools 2012-01-13 17:07:46 +01:00
Sebastien Bourdeauducq b60abfaa4a Convert -> convert 2012-01-05 19:27:45 +01:00
Sebastien Bourdeauducq 6664af73d1 uart: new design using FHDL and bank (TX only, incomplete) 2011-12-18 00:29:37 +01:00
Sebastien Bourdeauducq 0e30d67fa3 Multiply system clock 2011-12-17 15:00:18 +01:00
Sebastien Bourdeauducq 411e1af980 Proper reset generation 2011-12-16 22:25:26 +01:00
Sebastien Bourdeauducq ca68097ef6 Pay a bit more attention to PEP8 2011-12-16 16:02:49 +01:00