fb4f881857
.gitignore: ignore tilde files
2019-04-23 09:10:11 +02:00
535d86727a
targets/minispartan6: use S6PLL in CRG
2019-04-23 06:44:29 +02:00
40342404f2
cores/clock: add divclk_divide_range on S6PLL/S6DCM
2019-04-23 06:43:48 +02:00
0d282f38f9
cores/clock: use common XilinxClocking class for all Xilinx clocking modules
2019-04-23 06:35:39 +02:00
83699ea0a5
cores/clock: add initial Spartan6 PLL/DCM support
2019-04-23 06:23:00 +02:00
eff141da2d
build: add git version (sha-1) used to create the scripts
2019-04-23 06:03:12 +02:00
cc141a64b9
build: scripts are generated by LiteX
2019-04-23 05:38:33 +02:00
115c842ef0
build/xilinx/vivado: cleanup pull request #170
2019-04-23 05:33:56 +02:00
3b24b8d5b4
Merge pull request #170 from ldoolitt/master
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build/xilinx/vivado: only try Xilinx setup if vivado is not already i…
2019-04-23 05:26:54 +02:00
fda18fd6ef
build/xilinx/vivado: only try Xilinx setup if vivado is not already in the path
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Only affects the non-Windows code path.
Uses python distutils, already used elsewhere.
2019-04-22 15:42:31 -07:00
7d278854d5
global: switch to VexRiscv as the default CPU
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VexRiscv can now replace LM32 for almost all usecases and we now have better
software support with RISC-V.
2019-04-22 09:41:07 +02:00
28d80bd641
ci: fix test_targets/test_simple
2019-04-22 08:53:43 +02:00
b7f53fb93c
test: remove waveforms generation
2019-04-22 08:41:28 +02:00
e98ac680c1
travis: simplify, enable and add RISC-V toolchain to build targets
2019-04-22 08:32:00 +02:00
8c78997089
boards/platforms: add separators, cleanup imports
2019-04-21 00:44:23 +02:00
cb8c26d1b8
boards/platforms: provide only one default programmer per platform.
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create_programmer is not really longer used, so try to keep it simple.
2019-04-21 00:17:03 +02:00
e1d202df02
boards/platforms/kc705: only keep Vivado support
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There is no reason still using ISE on 7-Series.
2019-04-21 00:04:56 +02:00
53c7be6e46
boards: always define timing constraints the same way (1e9/freq_mhz)
2019-04-20 23:56:27 +02:00
02ffbed5e3
boards/targets/ulx3s: allow running test_targets on it
2019-04-20 23:47:05 +02:00
5a1925df2e
boards/targets: add keep attribute directly in crg
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This makes it systematic and avoid having to add it later.
2019-04-20 23:43:44 +02:00
67a79d7c92
Merge pull request #167 from xobs/network-flag-check
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litex_server: check socket flags exist before using them
2019-04-20 12:23:24 +02:00
f71b8d4f57
litex_server: check socket flags exist before using them
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Some flags are only available on certain platforms. Verify these flags
exist prior to using them when opening a socket.
See
https://stackoverflow.com/questions/14388706/socket-options-so-reuseaddr-and-so-reuseport-how-do-they-differ-do-they-mean-t
for more information
Signed-off-by: Sean Cross <sean@xobs.io>
2019-04-20 17:28:26 +08:00
9ee6c35b42
tools: move from litex.soc.tools to litex.tools and fix usb.core import
2019-04-20 10:44:53 +02:00
49fd93ae83
Merge pull request #165 from xobs/vexriscv-cpu-reset-address
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Vexriscv cpu reset address
2019-04-19 19:16:16 +02:00
ca6065a6a1
Merge pull request #164 from xobs/litex-usb-server
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Litex usb server support
2019-04-19 19:14:15 +02:00
c69183648f
utils: litex_server: add usb support
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Add `--usb` and associated arguments to create a litex bridge over
USB. This makes use of the new CommUSB module.
Signed-off-by: Sean Cross <sean@xobs.io>
2019-04-19 18:02:42 +01:00
9dd59d6301
tools: remote: add usb communications protocol
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This adds a USB communications protocol to the suite of litex-supported
wishbone bridge protocols.
Signed-off-by: Sean Cross <sean@xobs.io>
2019-04-19 17:29:50 +01:00
9cbed91b3e
soc/interconnect/axi: add AXIBurst2Beat
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Converts AXI bursts commands to AXI beats.
2019-04-19 12:13:16 +02:00
5a8115d9e1
soc/interconnect/avalon: add description
2019-04-19 11:43:15 +02:00
c780fb22b7
Merge branch 'master' of https://github.com/enjoy-digital/litex
2019-04-19 16:47:55 +08:00
fa95608694
soc/integration/soc_zynq: fix HP0 connections
2019-04-19 10:21:56 +02:00
a78ca2de92
build/xilinx/vivado: only set library for vhdl files (not supported for verilog/system-verilog)
2019-04-19 09:18:25 +02:00
e2cf45b8a9
cpu: vexriscv: allow cpu_reset_address to be overridden
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Allow the cpu_reset_address value to be overridden, for example allowing
it to be a signal. That way the reset address can be modified after
synthesis, in dual-core or debug situations.
Signed-off-by: Sean Cross <sean@xobs.io>
2019-04-19 13:04:57 +08:00
a92e90b215
soc/interconnect: add avalon with converters to/from native streams
2019-04-18 18:42:29 +02:00
d860eeea4f
Merge pull request #162 from antmicro/full-conf-vexriscv
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Add full and full_debug CPU variant of VexRiscv
2019-04-17 19:01:55 +02:00
ce81a39ce9
Merge pull request #163 from gsomlo/gls-verilated-cmdargs
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build/sim/core: Initialize Verilator commandArgs
2019-04-17 18:59:28 +02:00
e1683078ec
build/sim/core: Initialize Verilator commandArgs
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Required when DUT is using plusargs. Prevents Verilator simulation
from crashing with "Verilog called $test$plusargs or $value$plusargs
without testbench C first calling Verilated::commandArgs(argc,argv)".
2019-04-17 10:39:35 -04:00
40de01bcb0
vexriscv: Add full and full_debug CPU variant
2019-04-17 09:09:35 +02:00
017147c623
build/altera: switch to sdc constraints, add add_false_path_constraints method
2019-04-16 16:57:23 +02:00
1275e2f150
build/xilinx/vivado: set quiet property on MultiReg/AsyncResetSynchronizer constraints
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MultiReg/AsyncResetSynchronizer are not necessarily present in all design, set
quiet property to avoid generating false warnings.
2019-04-15 16:48:47 +02:00
c252972bef
soc/cores/clock: add divclk_divide/vco_margin support on S7/Ultrascale
2019-04-15 11:36:42 +02:00
f986974d60
soc/cores/clock: improve presentation
2019-04-15 10:57:00 +02:00
538ca59ab6
build/xilinx/vivado: round period constraints to lowest picosecond
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Vivado will do the opposite if we don't do it, with this change we ensure the applied period constraints will always be >= to the requested constraint.
2019-04-15 10:51:17 +02:00
66a74b1579
Merge pull request #161 from enjoy-digital/litex_server_arguments
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litex_server: refactor parameters and to allow setting bind address
2019-04-15 08:24:28 +02:00
a2bc4bb777
litex_server: set socket.SO_REUSEPORT to avoid waiting 60s in case of unclean termination
2019-04-15 08:23:27 +02:00
be99083e2b
litex_server: add message and exit when mandarory arguments are missing.
2019-04-14 14:00:35 +02:00
db11aec961
litex_server: allow setting bind port, remove auto-incrementing on bind_port
2019-04-14 12:48:49 +02:00
76bc57851b
litex_server: refactor parameters and to allow setting bind address
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In some cases, it can be useful to bind to "0.0.0.0" instead of "localhost".
While adding bind address support, parameters passing has also been refactored
to ease adding parameters in the future.
2019-04-14 09:00:08 +02:00
13a76ec7fb
software/libnet/microudp: simplify txbuffer managment
2019-04-12 18:47:31 +02:00
3441eb05cb
software/libnet/microudp: cleanup eth_init
2019-04-12 17:15:09 +02:00
Vamsi K Vytla
Florent Kermarrec
Michael Betz
Larry Doolittle
Sean Cross
Gabriel L. Somlo
Joanna Brozek