ffc342f49c
Merge pull request #11 from mithro/file-dont-change
...
Only require rebuild on actual changes
2016-12-17 14:43:34 +01:00
58b1eff819
Merge pull request #10 from mithro/etherbone
...
Patches to make it easier to work with Etherbone
2016-12-17 14:43:10 +01:00
1f6dc446d2
Allow CSRElement objects to be autocompleted.
2016-12-17 14:14:53 +01:00
722edfe9e8
Provide csr_data_width via the constants.
2016-12-17 14:14:53 +01:00
8bccd2d988
bios: Include dependency rebuild info.
2016-12-17 14:14:14 +01:00
46bbec5494
main.o is not a phony target.
2016-12-15 19:56:58 +01:00
4522157ddd
Use write_to_file helper.
2016-12-15 19:51:36 +01:00
8179a9ea2e
Don't modify file if contents hasn't changed.
2016-12-15 19:14:12 +01:00
9d716def9d
Make the csv directory if it doesn't exist.
2016-12-15 17:19:51 +01:00
8b5166f294
litex/boards: add machxo3 starter kit platform
2016-12-02 17:28:32 +01:00
873e50430e
litex/build: move xcf_template to platform (xcf is specific to platform)
2016-12-02 17:23:40 +01:00
daa9473809
soc/software/bios/main: revision command becomes ident
2016-11-30 15:45:06 +01:00
0f57451f30
soc/software/bios: remove dataflow
2016-11-30 15:44:30 +01:00
460185fa8e
litex_term: nicer progress bar
2016-11-30 15:36:13 +01:00
4f3ce6db2b
build/xilinx/vivado: fix settings source on linux
2016-11-30 15:28:38 +01:00
7bb2be41e8
Merge pull request #9 from mithro/vprintf-fix
...
libbase: Adding missing vprintf function.
2016-10-30 09:43:43 +01:00
29112c67e9
Merge pull request #7 from mithro/master
...
soc/software/Makefile: Fix Makefile depend generation.
2016-10-30 09:43:27 +01:00
548fd33d20
libbase: Adding missing vprintf function.
...
Fixes #8 .
```
int vprintf(const char *format, va_list ap);
The functions vprintf(), vfprintf(), vsprintf(), vsnprintf() are equivalent to
the functions printf(), fprintf(), sprintf(), snprintf(), respectively, except
that they are called with a va_list instead of a variable number of
arguments.
```
2016-10-30 16:25:06 +11:00
35ba9cf735
soc/software/Makefile: Fix Makefile depend generation.
...
Previously the flags were not actually set and the *.d files were never
actually generated.
2016-10-28 01:25:47 +11:00
7a9cf57cfe
boards/targets/sim: fix
2016-10-14 17:49:04 +02:00
677243bd8c
ElasticBuffer: infer reset
2016-10-14 09:43:09 +02:00
4362e5c528
gen/genlib/cdc: add ElasticBuffer
2016-10-13 17:04:39 +02:00
b74132f563
boards/platforms: add papilio_pro
2016-09-01 16:27:49 +02:00
99f2e31b2e
soc/tools/remote: allow direct use of comm_udp and some fixes
2016-07-18 17:04:58 +02:00
d59757eb4a
build/xilinx/ise: remove debug print
2016-06-29 23:32:43 +02:00
8efd57f766
setup.py: remove litex_client from console_scripts, we just need to import RemoteClient in our test scripts
2016-06-29 23:29:45 +02:00
9499147bd4
build/xilinx/ise: fix top name
2016-06-29 23:22:57 +02:00
3bb2bc35e2
boards/targets/sim: desactivate refresh for simulation
2016-06-20 16:00:19 +02:00
f193873bb8
soc/tools/remove/comm_uart: limit write bursts to 8 32bits words
2016-05-30 16:16:05 +02:00
6a35337a09
gen/sim/vcd: allow continous update of vcd file and dynamic signals
...
With continous update, VCD header needs to be writen at the beginning of the simulation.
When a new signal is created, we rewrite the header and the content.
2016-05-28 10:25:48 +02:00
fa7ac6c9a2
build/sim/dut_tb: add bottom line on surface to show frame count
2016-05-23 10:20:05 +02:00
65f74959b3
gen/sim/core: add Display support
2016-05-18 15:47:10 +02:00
6fe3e1237d
gen/fhdl/structure: fix Display
2016-05-18 12:41:29 +02:00
36fd466324
build/sim/dut_tb: rename needs to wait
2016-05-12 15:39:51 +02:00
e890a566a9
buid/sim: add vga framebuffer with SDL
2016-05-04 20:17:02 +02:00
55c9c653e0
adapt to litedram changes
2016-05-04 00:59:02 +02:00
7a7b9420e6
soc/integration/soc_dram: sync with litedram
2016-05-03 19:44:33 +02:00
dca8b3c92e
boards/targets/sim: update litedram
2016-05-01 10:26:21 +02:00
69f0035315
gen/fhdl: add Display for debug in simulation
2016-04-29 23:03:43 +02:00
e79b2e3fef
boards/targets: SDRAM modules are now litedram.modules
2016-04-29 19:05:23 +02:00
3d71ba6e66
targets: remove sdram_controller_type parameter (minicon removed)
2016-04-29 17:51:16 +02:00
8c7332e75e
soc/integration/soc_sdram: use new LiteDRAM names
2016-04-29 17:40:55 +02:00
dc52d33fba
soc_sdram: remove minicon support (we will make lasmicon more configurable to reduce ressource usage)
2016-04-29 16:24:24 +02:00
44d766c09f
software/sdram: cleanup artix7 init
2016-04-29 15:55:10 +02:00
5fb0fe925e
setup.py: fix version (0.1)
2016-04-29 14:39:14 +02:00
66362b1280
move sdram code to litedram ( https://github.com/enjoy-digital/litedram )
2016-04-29 07:45:15 +02:00
42767286ca
gen/fhdl/verilog: add do in reserved_keywords
2016-04-27 17:43:25 +02:00
80d673e502
soc/integration/soc_sdram: always generate L2_SIZE constant
2016-04-27 12:34:18 +02:00
4e451a78d6
soc/software/bios/sdram: add sdrlevel_artix7 (bitslip and delays have to be found manually)
2016-04-27 12:33:44 +02:00
ab8569916b
boards/platforms/arty: use 1.5V and the 16bits instead of only 8bits
2016-04-26 23:29:35 +02:00
enjoy-digital
Tim 'mithro' Ansell
whitequark
Robert Jordens