Charles Papon
|
401be6ca83
|
Reorganize project
|
2017-03-16 13:14:25 +01:00 |
|
Charles Papon
|
bf5bebda08
|
PcManager now drive PC asyncronously (use 1 cycle less in jump)
Fix bypass logic when read/write r0
Disable REGFILE_WRITE_VALID in decod stage when r0 is written
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2017-03-15 21:10:44 +01:00 |
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Charles Papon
|
83232e9860
|
Faster pipeline arbitration logic (200 Mhz on cyclone IV c6)
Branch plugin with jump in execute or memory stages (parameter)
|
2017-03-15 20:02:56 +01:00 |
|
Charles Papon
|
c6610ea454
|
Fix halt arbitrations
|
2017-03-15 17:14:58 +01:00 |
|
Charles Papon
|
11797fbb6e
|
Add sim performance print
|
2017-03-14 23:25:04 +01:00 |
|
Charles Papon
|
70d910e7d7
|
Load/Store pass Riscv-Tests
|
2017-03-14 23:00:24 +01:00 |
|
Charles Papon
|
7065ed5d93
|
All base instruction pass Riscv-Test (load/store not tested)
|
2017-03-14 20:13:35 +01:00 |
|
Charles Papon
|
ad6964f0bb
|
Classify tests
Riscv-test integration wip
|
2017-03-14 00:42:48 +01:00 |
|
Charles Papon
|
df99a0d963
|
Better decoding
|
2017-03-13 18:30:37 +01:00 |
|
Charles Papon
|
e36c90af03
|
Add decoder bench
|
2017-03-13 16:17:57 +01:00 |
|
Charles Papon
|
9fc82c9736
|
Pass verilator simple literal, add, jump
|
2017-03-12 20:12:40 +01:00 |
|
Dolu1990
|
ec4837a744
|
wip
|
2017-03-12 12:39:33 +01:00 |
|
Dolu1990
|
cb1b73bc2b
|
Add branch
|
2017-03-11 19:07:08 +01:00 |
|
Dolu1990
|
23abdb7f95
|
Add hazard tracking plugin
|
2017-03-11 16:45:04 +01:00 |
|
Dolu1990
|
e58f28bc27
|
Add store/load
|
2017-03-11 15:35:56 +01:00 |
|
Dolu1990
|
fcb70a333f
|
WIP
|
2017-03-11 00:34:49 +01:00 |
|
Dolu1990
|
fc7e9a7730
|
wip
|
2017-03-09 01:07:55 +01:00 |
|
Dolu1990
|
130ed6345c
|
boot
|
2017-03-08 22:17:48 +01:00 |