Commit Graph

24 Commits

Author SHA1 Message Date
Dolu1990 2f8f4d5444 SpinalHDL 1.1.5 2018-03-13 15:45:56 +01:00
Dolu1990 53970dd284 SpinalHDL 1.1.4
Now the CsrPlugin is waiting that the memory/writeback stages are empty before reading/writing things
2018-03-05 14:34:59 +01:00
Dolu1990 3b3bbd48b9 SpinalHDL 1.1.3 => Now Verilog rom are emited into separated bin files 2018-01-20 18:29:33 +01:00
Dolu1990 9a89573942 SpinalHDL 1.1.2
Add Murax setup with Mul Div Barriel
2018-01-06 22:09:42 +01:00
Dolu1990 4ed19f2cc5 SpinalHDL 1.1.1 2017-12-30 03:36:57 +01:00
Dolu1990 0d39e38906 SpinalHDL 1.1.0 2017-12-28 13:49:39 +01:00
Dolu1990 3a913f0789 SpinalHDL 1.0.5 2017-12-22 23:18:34 +01:00
Dolu1990 7f2b2181c1 SpinalHDL 1.0.3 2017-12-19 21:21:16 +01:00
Dolu1990 37849b7a66 Spinal 1.0.2 sim update 2017-12-19 00:40:52 +01:00
Dolu1990 15463a6276 spinalhdl 1.0.1 2017-12-17 19:36:18 +01:00
Dolu1990 2259c9cb0f Add SpinalHDL sim (1.0.0) 2017-12-14 00:57:12 +01:00
Dolu1990 f10dabd253 SpinalHDL 0.11.5 update 2017-12-05 15:58:05 +01:00
Dolu1990 e1b86ea511 SpinalHDL 0.11.4 update 2017-12-01 11:19:23 +01:00
Dolu1990 ce6fd6d0aa Add VexRiscvAxi4 demo 2017-11-20 23:57:37 +01:00
Dolu1990 9f9ec823b8 SpinalHDL 0.11.2 2017-11-15 17:57:08 +01:00
Dolu1990 6c3fed3505 SpinalHDL 0.11.1 2017-11-15 16:44:42 +01:00
Dolu1990 ba42f71813 pass VexRiscv regressions 2017-10-30 14:29:25 +01:00
Charles Papon a37494f27f Set sbt organization to com.github.spinalhdl 2017-08-01 20:43:15 +02:00
Charles Papon 823ac353ff Add Murax SoC (very light, work on ice40) 2017-07-28 21:25:49 +02:00
Charles Papon a94343b98a Update to SpinalHDL 0.10.14 2017-06-17 15:15:19 +02:00
Charles Papon 11a63491bd Add YAML feature to store CPU info 2017-06-09 16:06:18 +02:00
Charles Papon 6b62d8da52 VexRiscv in Briey SoC is working on FPGA (including jtag debugging) 2017-05-29 21:17:14 +02:00
Dolu1990 fcb70a333f WIP 2017-03-11 00:34:49 +01:00
Dolu1990 130ed6345c boot 2017-03-08 22:17:48 +01:00