Dolu1990
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530554d19c
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fix fpu diagram
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2021-03-16 14:52:57 +01:00 |
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Dolu1990
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e23687c45d
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Handle ClockDomain improvements
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2021-03-16 14:46:30 +01:00 |
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Dolu1990
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02c572b6f1
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fpu improve FMax and add asyncronus regfile support
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2021-03-16 14:45:59 +01:00 |
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Dolu1990
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0d628b4706
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fpu add doc
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2021-03-16 14:44:31 +01:00 |
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Dolu1990
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5aa1f2e996
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fpu improve pipline cycles
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2021-03-15 17:27:14 +01:00 |
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Dolu1990
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341c159d06
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data cache relax assert into error
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2021-03-15 14:43:22 +01:00 |
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Dolu1990
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3a34b8dae2
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Merge branch 'dev' into fiber
# Conflicts:
# src/main/scala/vexriscv/demo/smp/VexRiscvSmpCluster.scala
# src/main/scala/vexriscv/plugin/MulPlugin.scala
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2021-03-15 10:35:02 +01:00 |
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Charles Papon
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ff4e5e4666
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wipe generator
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2021-03-11 18:02:02 +01:00 |
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Charles Papon
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adc37b269c
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FpuPlugin.pending is now 6 bits
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2021-03-11 13:06:50 +01:00 |
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Charles Papon
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845cfcb966
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DebugPlugin.fromBscane2 added
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2021-03-10 20:35:44 +01:00 |
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Charles Papon
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67d2f72a4b
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fiber sync
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2021-03-07 20:43:02 +01:00 |
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Dolu1990
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e384bfe145
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fiber update
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2021-03-05 22:04:20 +01:00 |
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Dolu1990
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fd234bbf9e
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fix cfu gen error
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2021-03-05 09:41:05 +01:00 |
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Dolu1990
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aee8841438
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CFU ensure that CFU_IN_FLIGHT do not produce false positive when the pipeline is stuck
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2021-03-05 09:41:05 +01:00 |
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Dolu1990
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0530d22a1d
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sync
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2021-03-04 16:06:18 +01:00 |
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Dolu1990
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caf1bde49b
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Add MuraxAsicBlackBox example
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2021-03-04 10:16:45 +01:00 |
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Dolu1990
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4bdab667cc
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fpu fix cmd / commit race condition
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2021-03-02 19:39:55 +01:00 |
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Dolu1990
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636d53cf63
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fpu now track commits using a counter per pipeline per port
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2021-03-02 16:13:12 +01:00 |
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Dolu1990
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81c193af1f
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Improve subnormal/normal rounding
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2021-02-26 16:32:42 +01:00 |
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Dolu1990
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de81da36eb
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Fpu fix a few div special cases
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2021-02-25 19:39:57 +01:00 |
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Dolu1990
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de09ed3fcb
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fpu added exact div/sqrt implementations using iterative approaches
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2021-02-25 15:28:38 +01:00 |
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Dolu1990
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be81cc1e0e
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CfuPlugin.response_ok removed
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2021-02-23 12:23:48 +01:00 |
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Dolu1990
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47673863fb
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fpu test cleaning
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2021-02-22 19:27:55 +01:00 |
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Dolu1990
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b1f4c06d4e
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fpu fix arbitration/lock bugs
add getVexRiscvRegressionArgs
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2021-02-22 19:27:26 +01:00 |
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Dolu1990
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a6e89fe05c
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fpu vex regression goldenModel can now assert FPU interface
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2021-02-19 17:55:56 +01:00 |
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Dolu1990
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3f226b758c
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fpu fix exception flag handeling
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2021-02-19 13:03:48 +01:00 |
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Dolu1990
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e504afbf18
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fpu integration wip, got mandelbrot to work in linux with no inline (crash when inlined)
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2021-02-19 11:26:28 +01:00 |
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Dolu1990
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8537d18b16
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fpu improve fmax
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2021-02-17 16:35:52 +01:00 |
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Dolu1990
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1e647f799c
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fpu Fix VexRiscv integration and add software f64 tests (pass)
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2021-02-17 12:33:27 +01:00 |
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Dolu1990
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06b7a91de4
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MulPlugin fix buffer interraction with partial regfile bypass
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2021-02-17 11:35:17 +01:00 |
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Dolu1990
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f180ba2fc9
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fpu double fixes
DataCache now support wide load/store
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2021-02-16 15:38:51 +01:00 |
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Dolu1990
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8b2a2afb6f
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VexRIscvSmpCluster add options
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2021-02-16 14:42:31 +01:00 |
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Dolu1990
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1752b9e6d6
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DataCache.toBmb with aggregation sync path pipelined
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2021-02-16 14:17:21 +01:00 |
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Dolu1990
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fe690528f7
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MulPlugin.outputBuffer feature added
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2021-02-16 14:16:57 +01:00 |
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Dolu1990
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3b99090879
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VexRiscvConfig.get added
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2021-02-16 14:15:20 +01:00 |
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Dolu1990
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7d3b35c32c
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fpu f64/f32 pass all tests
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2021-02-12 14:48:44 +01:00 |
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Dolu1990
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9a25a12879
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fpu add FCVT_X_X
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2021-02-11 17:40:35 +01:00 |
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Dolu1990
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82dfd10dba
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fpu fix f32 tests for f64 fpu
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2021-02-11 16:42:17 +01:00 |
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Dolu1990
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b6eda1ad7a
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fpu f64 load/store/mv/mul seems ok
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2021-02-11 16:07:47 +01:00 |
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Dolu1990
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e97c2de837
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fpu f64 wip
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2021-02-10 19:27:26 +01:00 |
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Dolu1990
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88dffc21f7
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fpu f64 wip
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2021-02-10 13:20:17 +01:00 |
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Dolu1990
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889cc5fde2
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fpu refractoring
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2021-02-10 12:16:56 +01:00 |
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Dolu1990
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1fe993ad10
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fpu fixed corner cases, FpuPlugin coupling, pass rv-test excepted div (accuracy), can run C sinf successfully
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2021-02-09 18:35:47 +01:00 |
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Dolu1990
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bf6a64b6b5
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fpu sgnj / fclass / fmv pass
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2021-02-08 15:29:50 +01:00 |
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Dolu1990
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bf0829231d
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fpu min max pass
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2021-02-06 14:08:21 +01:00 |
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Dolu1990
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008fadeaa9
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fpu eq lt le pass testfloat
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2021-02-06 13:20:27 +01:00 |
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Dolu1990
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6170243283
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fpu got exception flag right for add/sub/mul/i2f/f2i
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2021-02-05 16:24:14 +01:00 |
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Dolu1990
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f278900cbe
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VexRiscvSmpCluster can now set regfile read kind
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2021-02-05 11:09:18 +01:00 |
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Dolu1990
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0f1ca72171
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fix synthesis bench
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2021-02-04 12:43:31 +01:00 |
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Dolu1990
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936e5823dc
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fpu test wip
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2021-02-04 12:41:49 +01:00 |