Hardware
/
VexRiscv
mirror of https://github.com/SpinalHDL/VexRiscv.git
1
0
Fork 0
Code Issues Packages Projects Releases Wiki Activity
805 Commits 39 Branches 2 Tags 15 MiB
Commit Graph

805 Commits

Author SHA1 Message Date
Charles Papon 744b040c70 Sync CFU progress 2019-11-29 11:50:00 +01:00
Charles Papon 7ae218704e CsrPlugin now implement a IWake interface 
DebugPlugin now wake the CPU if a halt is asked to flush the pipeline
 2019-11-19 18:36:53 +01:00
Charles Papon 6d0d70364c Add BranchPlugin.decodeBranchSrc2 for branch target configs 2019-11-08 14:01:53 +01:00
Charles Papon 4fe7fa56c7 GenCustomInterrupt demo now enabled vectored interrupt 2019-11-07 19:55:26 +01:00
Charles Papon bb405e705b Add UserInterruptPlugin 2019-11-07 19:52:45 +01:00
Charles Papon 2bf6a536c9 Fix DBus AXI bridges from writePending counter deadlock 2019-11-03 16:44:09 +01:00
Charles Papon bd2787b562 RegFilePlugin project X0 against boot glitches if no x0Init but zeroBoot 2019-11-01 16:24:07 +01:00
Charles Papon b4c75d4898 Merge remote-tracking branch 'origin/dev' into dev 2019-10-11 00:25:37 +02:00
Charles Papon a2b49ae000 Fix CFU arbitration, add CFU decoder, CFU now redirect custom-0 with func3 2019-10-11 00:25:22 +02:00
Charles Papon 310c325eaa IBusCached add Keep attribut on the line loader to avoid Artix7 block ram merge, but do not seem to have effect 2019-10-11 00:24:21 +02:00
Charles Papon 711eed1e77 MulPlugin add withInputBuffer feature and now use RSx instead of SRCx 2019-10-11 00:23:29 +02:00
Charles Papon 3fc0a74102 Add Keep attribut on dBusCached relaxedMemoryTranslationRegister feature 2019-10-11 00:22:44 +02:00
Charles Papon 51d22d4a8c Merge remote-tracking branch 'origin/cfu' into dev 2019-10-10 15:00:43 +02:00
Charles Papon 319d162f67 Merge remote-tracking branch 'origin/tigthlyCoupled' into dev 2019-10-03 12:33:27 +02:00
Charles Papon 5df56bea79 Allow getDrivingReg to properly see i$ decode.input(INSTRUCTION) register 
(used to inject instruction from the debug plugin)
 2019-10-03 00:20:33 +02:00
Charles Papon be18d8fa5a CSR access enables are also impacted by the MMU memory access 2019-09-21 10:28:52 +02:00
Charles Papon 88eb8e4e47 Fix Artix7 FMax, my apologies for that, was due to a bad scripting using Kintex 7 instead 2019-09-16 14:22:33 +02:00
Charles Papon 6ed41f7361 Improve CSR FMax 2019-09-16 13:53:55 +02:00
Charles Papon d94cee13f0 Add dummy decoding, exception code/tval 
Add Cpu generation code
Add support for always ready rsp
 2019-09-05 19:06:28 +02:00
Charles Papon 5ac443b745 Manage cases where a rsp buffer is required 2019-09-05 10:41:45 +02:00
Dolu1990 6951f5b8e6 CfuPlugin addition 2019-09-05 10:41:45 +02:00
Dolu1990 84602f89b0 Merge pull request #80 from antmicro/fix_litex_target 
Fix handling LiteX uart and timer.
 2019-09-05 10:41:45 +02:00
Dolu1990 0efcaa505d Merge pull request #79 from antmicro/litex_target 
Litex target
 2019-09-05 10:41:45 +02:00
Mateusz Holenko 86f5af5ca9 Fix handling LiteX uart and timer. 2019-09-05 10:41:45 +02:00
Charles Papon 94f1707d65 Merge branch 'dev' 2019-09-05 10:41:45 +02:00
Mateusz Holenko 8813e071bc Add `litex` target 
Use configuration from the `csr.h` file
generated dynamically when building a LiteX platform.
 2019-09-05 10:41:45 +02:00
Mateusz Holenko 64a2815544 Create makefile targets 
Allow to change build target without modifiying the sources.
In order to keep compatibilty `sim` target is built by default.
 2019-09-05 10:41:45 +02:00
Mateusz Holenko e76435c6c6 Allow to set custom DTB/OS_CALL addresses 
Setting those from command line during compilation allows
to create a custom setup without the need of modifying the
sources.
 2019-09-05 10:41:45 +02:00
Mateusz Holenko c8280a9a88 Allow to set custom RAM base address for emulator 
This is needed when loading the emulator to RAM
with an offset.
 2019-09-05 10:41:45 +02:00
Charles Papon b65ef189eb sync with SpinalHDL SDRAM changes 2019-08-29 16:03:20 +02:00
Charles Papon a2569e76c0 Update sdram ctrl package 2019-07-08 11:23:48 +02:00
Charles Papon 624c641af5 xip refractoring 2019-06-28 10:23:39 +02:00
Charles Papon b2e06ae198 Back into unreleased SpinalHDL 2019-06-17 17:19:11 +02:00
Charles Papon 1257b056dc Revert "test only dynamic_target for intensive test" 
This reverts commit 635ef51f82.
 2019-06-16 18:24:59 +02:00
Charles Papon 12c3ab16ae Update readme perf 2019-06-16 18:07:04 +02:00
Charles Papon 635ef51f82 test only dynamic_target for intensive test 2019-06-16 17:43:07 +02:00
Charles Papon 9656604848 rework dynamic_target failure correction 2019-06-16 17:42:39 +02:00
Charles Papon 4cf7e5b98f SpinalHDL 1.3.6 2019-06-16 00:42:59 +02:00
Charles Papon 60c9c094a7 Merge remote-tracking branch 'origin/rework_jump_flush' into dev 2019-06-15 18:09:38 +02:00
Charles Papon 46e9d5566a Merge branch 'rework_jump_flush' 2019-06-15 18:05:04 +02:00
Charles Papon 7c3c4e8c81 Update readme benches 2019-06-15 14:23:09 +02:00
Charles Papon a3a0c402bc Remove broken freertos test and add zephyr instead 2019-06-15 10:46:10 +02:00
Charles Papon 617f4742cd Fix dynamic branch prediction correction on misspredicted fetch which are done on a 32 bits instruction crossing two words in configs which have at least 2 cycle latency fetch 2019-06-14 08:13:22 +02:00
Charles Papon d603de1bfe Fix recent changes 2019-06-13 16:55:24 +02:00
Charles Papon c8ab99cd0b Cleaning and remove BlockQ regression 2019-06-12 00:00:38 +02:00
Charles Papon 21ec368927 Fix DYNAMIC_TARGET by fixing decode PC updates 2019-06-11 19:56:33 +02:00
Charles Papon afbf0ea777 Fix regression makefile 2019-06-11 01:05:49 +02:00
Charles Papon 066ddc23e6 Add regression concurrent os executions flag to avoid running debug plugin tests 2019-06-11 00:22:38 +02:00
Charles Papon 21c8933bbb Fix DYNAMIC_TARGET prediction correction in BranchPlugin 2019-06-11 00:12:29 +02:00
Charles Papon 5b53440d27 DYNAMIC_TARGET prediction datapath/control path are now splited 2019-06-10 22:20:32 +02:00