Dolu1990
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7649157946
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d$ toBmb increase aggregation timer
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2023-04-13 16:52:20 +02:00 |
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Dolu1990
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051080e060
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CsrPlugin now implement dummy HPM
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2023-04-13 16:51:44 +02:00 |
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Dolu1990
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d966c4efe1
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fix #328 medeleg EBREAK added
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2023-04-10 13:02:51 +02:00 |
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Dolu1990
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320867e135
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sync
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2023-04-04 18:11:33 +02:00 |
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Dolu1990
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95e61a7951
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Revert CfuPlugin
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2023-04-04 11:47:49 +02:00 |
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Dolu1990
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cb0bacfce9
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implement dummy pmp as 1.10 spec says
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2023-03-31 10:12:52 +02:00 |
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Dolu1990
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b4d5a315cf
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CsrPlugin implement dummy pmp if no pmp is there
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2023-03-31 10:11:53 +02:00 |
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Dolu1990
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9c2e05cce0
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Ensure that fence.i wait d$ inflight write and reschedule the next instruction
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2023-03-29 14:56:53 +02:00 |
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Dolu1990
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e357420d11
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CsrPluginConfig more var
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2023-03-29 11:10:51 +02:00 |
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Dolu1990
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a33380894c
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sync
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2023-03-27 09:57:55 +02:00 |
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Dolu1990
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e754c5c3a0
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cleanup IBusDBusCachedTightlyCoupledRam
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2023-03-27 08:23:32 +02:00 |
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Dolu1990
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eeb65ed1c0
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VexRiscvBmbGenrator now use relaxedReset
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2023-03-24 08:39:07 +01:00 |
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Dolu1990
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c69852c0cc
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ClockDomainResetGeneratorIf introduction
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2023-03-23 16:57:10 +01:00 |
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Dolu1990
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8195bec788
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privSpec now check FPU dirty flag
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2023-03-23 11:24:38 +01:00 |
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Dolu1990
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8c5071ce42
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VexRiscvSmpCluster fullCsr improvement
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2023-03-23 08:53:41 +01:00 |
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Dolu1990
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b01490b5f3
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Implement counteren (1.10+ spec)
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2023-03-23 08:53:10 +01:00 |
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Dolu1990
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570720fdd8
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Cfu add enableInit option
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2023-03-22 17:13:47 +01:00 |
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Dolu1990
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0e59a56bd1
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add privSpec test
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2023-03-22 16:25:23 +01:00 |
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Dolu1990
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bba022b746
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fix a few csr related WARL (minor)
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2023-03-22 16:25:03 +01:00 |
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Dolu1990
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385a195d16
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few more var parameters
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2023-03-22 12:58:43 +01:00 |
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Dolu1990
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a755d839b3
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Add VexRiscvSmpClusterGen csrFull (wip)
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2023-03-22 11:07:18 +01:00 |
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Dolu1990
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5b47564024
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A few plugins config are now var
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2023-03-22 11:06:56 +01:00 |
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Dolu1990
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4972a27ae9
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More verbose main.cpp on failure, fix C.ADDSP regfile initialisation
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2023-03-22 11:06:23 +01:00 |
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Charles Papon
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0aa8cb11e0
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BranchPlugin do not use casez anymore
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2023-03-15 17:43:44 +08:00 |
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Charles Papon
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13061b8b2e
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debug unavailable is now BufferCC
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2023-03-15 09:50:09 +08:00 |
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Charles Papon
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876222d886
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Fix FPU access port instanciation when not needed
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2023-03-14 15:23:04 +08:00 |
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Charles Papon
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25eda80fee
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FpuTest document how to install berkley testfloat
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2023-03-10 14:46:21 +08:00 |
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Charles Papon
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94f19032f0
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FpuPlugin.access port added
Privileged debug access added
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2023-03-10 14:44:14 +08:00 |
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Charles Papon
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6be1531d36
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Fpu will not trap anymore on debug access if fs==0
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2023-03-10 09:17:01 +08:00 |
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Charles Papon
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1179c6551f
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Fix #321 #322 #333 FPU precision removal
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2023-03-08 16:00:22 +08:00 |
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Charles Papon
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f11c642cd6
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CfuPlugin encoding can now specify cmd/rsp less instruction
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2023-03-07 16:49:07 +08:00 |
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Charles Papon
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3cf8508db1
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DBus coupled timings improvement
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2023-03-05 20:31:40 +08:00 |
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Charles Papon
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153445ff21
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Fix CFU / FPU decoder stage fork on illegal instruction
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2023-03-05 20:29:53 +08:00 |
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Dolu1990
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cf70bc6b1f
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fix last push
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2023-03-03 14:20:12 +01:00 |
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Dolu1990
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b03b00a5c4
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Improve d$ coupled timings
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2023-03-03 14:13:51 +01:00 |
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Dolu1990
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5493c55ab0
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Alows Fetcher to have multiple debug injection ports
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2023-03-03 09:06:20 +01:00 |
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Dolu1990
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5f67075e30
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Fix FPU with F64 support, not removing mantissa precision from F32 #317
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2023-03-01 13:56:25 +01:00 |
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Dolu1990
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6f76a45e7d
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update mmu test
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2023-02-23 15:54:39 +01:00 |
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Dolu1990
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d7e9c726c3
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Fix datacache initial flush
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2023-02-23 14:42:21 +01:00 |
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Dolu1990
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c5689e512c
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CsrPlugin now provide regression args
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2023-02-23 12:00:25 +01:00 |
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Dolu1990
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a40d5f19b2
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Fix MMU A and D flag handeling
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2023-02-23 12:00:08 +01:00 |
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Dolu1990
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344b2d4eda
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TestIndividual supervisor missing CSR=yes
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2023-02-23 11:59:13 +01:00 |
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Dolu1990
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9605b663bf
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D$ now support thightly coupled ram.
Add IBusDBusCachedTightlyCoupledRam plugin
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2023-02-22 15:26:14 +01:00 |
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Dolu1990
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220b599c9a
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Fix d$ invalidation when the mmu is enabled
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2023-02-22 13:16:02 +01:00 |
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Dolu1990
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15a665af53
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fix too early
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2023-02-19 09:51:18 +01:00 |
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Dolu1990
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d078297496
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fix too early
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2023-02-19 09:48:59 +01:00 |
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Dolu1990
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a780eec616
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Merge branch 'debug-debug' into dev
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2023-02-13 10:04:41 +01:00 |
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Dolu1990
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33e820bdf9
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FPU now implement a less pessismitic dirty logic
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2023-02-08 15:16:53 +01:00 |
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Dolu1990
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3ae51cdeb8
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Fix fpu csr access on fs===0 now also trap
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2023-02-08 14:44:04 +01:00 |
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Dolu1990
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692f604dd5
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Fix VexRiscvSmpClusterGen without linux debug minimal features
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2023-02-08 11:28:21 +01:00 |