Dolu1990
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485f35a1b5
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IBusCachedPlugin default is two cycle cache with single cycle ram.
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2018-05-24 13:46:31 +02:00 |
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Dolu1990
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2f8ccc55b6
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Fix branch plugin decode prediction exception by using the instruction decoder
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2018-05-24 12:52:00 +02:00 |
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Dolu1990
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a53f8fdc35
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Clean configs
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2018-05-23 16:57:32 +02:00 |
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Dolu1990
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eb5bc4a791
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Fix RVC decompressor (ALU immediats)
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2018-05-22 17:23:20 +02:00 |
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Dolu1990
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ff760a0bf0
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DYNAMIC_TARGET branch prediction back for not compressed ISA (PASS)
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2018-05-21 13:45:08 +02:00 |
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Dolu1990
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6c47a3b2a3
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update key
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2018-05-17 19:07:58 +02:00 |
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Dolu1990
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e63e57981e
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travis test upload
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2018-05-17 19:04:35 +02:00 |
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Dolu1990
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042962c1ae
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Fix travis
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2018-05-17 18:56:31 +02:00 |
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Dolu1990
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938ed6abf6
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Add bintraykey
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2018-05-17 18:52:21 +02:00 |
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Dolu1990
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81790c32b8
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Add travis
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2018-05-17 18:43:52 +02:00 |
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Dolu1990
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7ffbfab312
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Reintroduce MMU feature (pass tests)
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2018-05-16 20:32:12 +02:00 |
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Dolu1990
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35fbf177e2
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Update to SpinalHDL 1.1.6
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2018-05-16 12:12:09 +02:00 |
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Dolu1990
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c8cec59f1d
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Update IBusCachedPlugin parameters
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2018-05-16 12:11:53 +02:00 |
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Dolu1990
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3b54ecf303
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Restore two cycle instruction cache features
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2018-05-15 23:03:33 +02:00 |
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Dolu1990
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4e7152ae5a
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IcestormFlow add ultraplus support
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2018-05-14 20:18:53 +02:00 |
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Dolu1990
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df3d9ccb13
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rework IBusSimplePlugin parameters
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2018-05-14 10:31:40 +02:00 |
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Dolu1990
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c0271d382f
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More assertion (csrPlugin)
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2018-05-14 10:13:44 +02:00 |
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Dolu1990
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9caa7163ae
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IBusSimplePlugin add relaxedBusCmdValid feature
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2018-05-14 10:04:19 +02:00 |
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Dolu1990
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610bd01f3b
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remove rspStageGen
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2018-05-14 09:21:28 +02:00 |
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Dolu1990
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7b37669a0f
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Add exception catch to iBusSimplePLugin (pass)
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2018-05-09 18:43:48 +02:00 |
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Dolu1990
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acccbf40e2
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RVC debug pass tets
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2018-05-09 00:28:14 +02:00 |
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Dolu1990
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0056da1342
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DebugPlugin work
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2018-05-08 02:01:34 +02:00 |
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Dolu1990
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e65757e34c
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wip before moving the fetchHalt
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2018-05-06 16:38:00 +02:00 |
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Dolu1990
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294293cb70
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Reintroduce debug plugin (instruction injector need optimisations)
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2018-05-05 23:05:32 +02:00 |
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Dolu1990
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a50fbf0d7a
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Fix IBusCachedPlugin Pass all dhrystone tests
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2018-04-30 13:35:17 +02:00 |
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Dolu1990
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558af595a1
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Add ice40 synthesis results
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2018-04-26 13:14:37 +02:00 |
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Dolu1990
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bdcf3f6234
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Add HexTools and add a Briey main which load the ram
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2018-04-26 10:27:39 +02:00 |
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Dolu1990
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cfc324aa0f
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Allow csr mtvec to not have reset values
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2018-04-24 23:33:48 +02:00 |
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Dolu1990
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a9cbc48eb2
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PcManagerPlugin is can now handle an external reset vector signal
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2018-04-24 23:11:11 +02:00 |
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Dolu1990
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c7d852c497
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Merge remote-tracking branch 'origin/Wishbone'
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2018-04-22 12:15:25 +02:00 |
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Dolu1990
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978eb9b6b2
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DBusCachedPlugin add CSR info
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2018-04-22 11:46:01 +02:00 |
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Dolu1990
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74f2a4194a
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Add ExternalInterruptArrayPlugin
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2018-04-20 17:56:21 +02:00 |
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Dolu1990
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6598e82920
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wishbone => word address, not byte address
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2018-04-19 11:22:06 +02:00 |
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Dolu1990
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455607b6b4
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Fix dBus IO access
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2018-04-18 14:11:59 +02:00 |
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Dolu1990
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6e59ddcc73
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Cached wishbone demo is passing regression tests
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2018-04-18 13:51:33 +02:00 |
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Dolu1990
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b37fc3fcc8
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Add VexRiscv Wishbone demo for sim (generation ok)
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2018-04-18 12:54:20 +02:00 |
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Dolu1990
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a66efcb35b
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Add wishbone support for i$ / d$ (not tested)
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2018-04-17 23:56:44 +02:00 |
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Dolu1990
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4440047fb6
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ICache compressed is working
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2018-04-16 10:34:18 +02:00 |
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Dolu1990
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76352b44fa
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wip
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2018-04-13 12:51:27 +02:00 |
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Dolu1990
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19d5d1ecf1
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wip
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2018-04-09 09:18:08 +02:00 |
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Dolu1990
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4dd2997ad5
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wip
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2018-04-09 09:12:30 +02:00 |
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Dolu1990
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e00c0750eb
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wip
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2018-04-03 18:37:05 +02:00 |
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Dolu1990
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d9f2e03753
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statuc prediction is fully funcitonnal
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2018-04-02 17:43:58 +02:00 |
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Dolu1990
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76ca852478
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Static prediction is fully functionnal
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2018-04-02 17:43:06 +02:00 |
Dolu1990
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bd4d1eeb01
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Update briey soc diagram
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2018-03-24 13:49:50 +01:00 |
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Dolu1990
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0919308a8f
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IBusSimplePlugin add relaxedPcCalculation
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2018-03-23 22:49:32 +01:00 |
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Dolu1990
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c48c7170e8
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Added many pipelining option into IBusSimplePlugin
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2018-03-23 19:07:03 +01:00 |
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Dolu1990
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925f6ae811
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Update README.md
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2018-03-22 15:25:40 +01:00 |
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Dolu1990
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cd4ffc2f3f
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Update README.md
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2018-03-22 15:24:56 +01:00 |
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Dolu1990
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7da85303dd
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Update README.md
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2018-03-22 14:40:08 +01:00 |