Commit Graph

987 Commits

Author SHA1 Message Date
Charles Papon 4ad1215873 Fix iBusSimplePlugin MMU integration 2020-02-21 13:28:42 +01:00
Charles Papon befc54a444 No more Fetcher flush() API as it can now be done via the decoder.flushNext 2020-02-21 13:28:29 +01:00
Charles Papon 32fade50e5 Fix fetcher decompressor when driving decode stage 2020-02-21 02:03:29 +01:00
Charles Papon 59508d5b57 Fix target branch prediction for RVC, all default configs pass dhrystone 2020-02-20 02:27:57 +01:00
Charles Papon a684d5e4d1 Rework/clean decompressor logic 2020-02-19 01:20:52 +01:00
Charles Papon a7440426fd Fix FetchPlugin redo gen condition
Fix injectorFailure reset
2020-02-18 01:00:11 +01:00
Charles Papon f63c4db469 Fix CsrPlugin pipeline liberator 2020-02-18 00:59:39 +01:00
Charles Papon 53a29e35e9 fix deleg external interrupt propagation time failure 2020-02-17 23:27:17 +01:00
Charles Papon e0cd9a6e06 clean iBusRsp redo 2020-02-17 22:45:34 +01:00
Charles Papon 0e0a568743 Apply DYNAMIC_TARGET correction all the time 2020-02-17 21:43:02 +01:00
Charles Papon e23295f06e Fix Fetcher pcValid pipeline 2020-02-17 19:29:41 +01:00
Charles Papon 9e75e2cb58 IBusFetcher disable pcRegReusedForSecondStage when using fetch prediction.
Fix some fetch flush
DYNAMIC_PREDICTION start to work again
2020-02-17 14:36:08 +01:00
Charles Papon 8be50b8e3d IBusFetcher now support proper iBusRsp.redo/flush 2020-02-17 12:50:12 +01:00
Charles Papon ebfa9e6577 Merge branch 'dev' into rework_fetch 2020-02-16 18:52:31 +01:00
Charles Papon 29f85a7ae2 Remove INSTRUCTION_READY
Add proper Fetcher.ibusRsp.flush
prediction are disabled yet
much is broken for sure, WIP
2020-02-16 18:44:10 +01:00
Charles Papon 0c255e2404 Merge branch 'compiler_plugin' into dev 2020-02-16 14:34:26 +01:00
Charles Papon 3d34d754a9 Remove usages of implicit string to B/U/S 2020-02-15 10:11:00 +01:00
Charles Papon d241f35625 Remove usages of implicit string to B/U/S 2020-02-15 10:10:04 +01:00
Charles Papon f1959ff830 smp spec typo 2020-02-15 00:26:11 +01:00
Charles Papon 6edab1eb34 Add SMP spec draft 2020-02-15 00:24:33 +01:00
Dolu1990 b728b60051
Merge pull request #113 from japm48/patch-2
Murax on arty_a7: fix inferred memory type
2020-02-12 23:27:51 +01:00
japm48 6547eefffd
Murax on arty_a7: fix mkdir error 2020-02-11 18:58:43 +01:00
Dolu1990 ecee7122a5
Merge pull request #112 from japm48/patch-1
Readme: fix spelling and made some clarifications
2020-02-11 18:51:45 +01:00
japm48 163611bd11
Murax on arty_a7: fix RAMB type on soc_mmi.tcl 2020-02-11 18:49:56 +01:00
japm48 fd961dccb5
Readme: fix spelling and made some clarifications 2020-02-11 18:18:39 +01:00
Charles Papon 10da093422 Fix sbt 2020-02-06 21:07:40 +01:00
Charles Papon 38a573a48c Update build.sbt 2020-02-03 13:35:55 +01:00
Charles Papon ee36c36fdd Merge branch 'masterPrerelease' 2020-01-31 11:37:04 +01:00
Charles Papon 390645e581 SpinalHDL 1.3.8 2020-01-29 23:20:35 +01:00
Charles Papon 5b8febb977 Revert "Revert "Merge branch 'master' into dev""
This reverts commit c01c256757.

Fix dBusCachedPlugin relaxedMemoryTranslationRegister when mmu translation is done in the execute stage
2020-01-29 22:37:09 +01:00
Charles Papon c01c256757 Revert "Merge branch 'master' into dev"
This reverts commit b5374433a5, reversing
changes made to f01da9c73b.
2020-01-29 15:20:13 +01:00
Charles Papon b5374433a5 Merge branch 'master' into dev 2020-01-29 12:50:41 +01:00
Dolu1990 ac79cc6fe6
Merge pull request #109 from sebastien-riou/arty
missing tcl files for Murax on Arty
2020-01-17 12:07:54 +01:00
sebastien-riou badc38d645 Merge remote-tracking branch 'origin/master' into arty 2020-01-17 00:54:19 +01:00
sebastien-riou 1fb1e358bb fix makefile clean target 2020-01-17 00:49:35 +01:00
sebastien-riou 2bcddd333d forced the commit of missing TCL files 2020-01-17 00:33:02 +01:00
Dolu1990 95ec47e5b8
Merge pull request #108 from sebastien-riou/arty
Murax on Arty A7-35
2020-01-16 23:21:29 +01:00
sebastien-riou 97b2838d18 Murax on Digilent Arty A7-35 2020-01-16 21:58:55 +01:00
sebastien-riou 195318b665
Merge pull request #1 from sebastien-riou/VXIP
Murax_xip: better pin names in scala, bootloader without magic word
2020-01-13 22:06:31 +01:00
sebastien-riou de9f704de2 better pin names in scala, bootloader without magic word 2020-01-13 21:58:08 +01:00
Charles Papon f01da9c73b CsrPlugin add printCsr 2020-01-13 20:44:55 +01:00
sebastien-riou 49f502aef4 Merge branch 'master' of github.com:sebastien-riou/VexRiscv 2020-01-12 19:52:59 +01:00
sebastien-riou bfb0b54f9b readme for XIP on Murax improved 2020-01-12 19:52:27 +01:00
Dolu1990 b66de1a3c0
Merge branch 'master' into master 2020-01-12 17:38:16 +01:00
sebastien-riou b866dcb07f XIP on Murax improvements 2020-01-12 16:08:14 +01:00
Dolu1990 061ebd1b2c
Fix murax xip bootloader 2020-01-12 13:27:45 +01:00
Charles Papon 4c7025b964 Fix xtval when no exception and read_only 2020-01-06 20:07:23 +01:00
Charles Papon 2a06907902 fix compilation 2019-12-24 01:09:55 +01:00
Charles Papon 3b494e97cd Moved KeepAttribute to spinal.lib 2019-12-24 00:43:36 +01:00
Charles Papon 052c8dd602 Fix inWfi naming, fix regressions 2019-12-20 00:21:55 +01:00