Charles Papon
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d5723968da
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Merge remote-tracking branch 'origin/master' into linux
# Conflicts:
# src/main/scala/vexriscv/plugin/IBusSimplePlugin.scala
# src/test/cpp/regression/main.cpp
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2019-04-12 16:26:08 +02:00 |
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Dolu1990
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b69c474fa2
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#60 user space reached
/sbin/init: error while loading shared libraries: libm.so.6: cannot stat shared object: Error 38
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2019-03-27 00:26:51 +01:00 |
Tom Verbeure
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1afad4f240
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Ignore vim backup files.
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2019-03-23 22:34:22 +00:00 |
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Dolu1990
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ccc3b63d7c
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Enable golden model check for all regressions
Need to implement missing CSR of the golden model
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2019-03-20 01:12:03 +01:00 |
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Dolu1990
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c26b7e15cf
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BranchPlugin exceptions are now risc-v compliance alligned
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2018-10-11 17:56:49 +02:00 |
Dolu1990
|
ce54fd78e4
|
wip
|
2018-07-07 11:40:02 +02:00 |
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Dolu1990
|
3b3bbd48b9
|
SpinalHDL 1.1.3 => Now Verilog rom are emited into separated bin files
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2018-01-20 18:29:33 +01:00 |
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Dolu1990
|
3a913f0789
|
SpinalHDL 1.0.5
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2017-12-22 23:18:34 +01:00 |
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Dolu1990
|
ebda7526b5
|
MuraxSim 1.0.0
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2017-12-17 17:57:09 +01:00 |
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Charles Papon
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54b06e6438
|
Add SIMD_ADD regression and config (show case)
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2017-08-08 18:19:02 +02:00 |
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Dolu1990
|
59e09ce269
|
Exclude TCL from the repo
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2017-07-16 18:24:28 +02:00 |
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Charles Papon
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f8678698fc
|
Briey improve AXI FMax
Faster debugginPlugin regression
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2017-06-11 11:52:59 +02:00 |
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Charles Papon
|
5e9da0f27a
|
Add self checked dhrystone test
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2017-03-18 12:32:14 +01:00 |
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Charles Papon
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9fc82c9736
|
Pass verilator simple literal, add, jump
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2017-03-12 20:12:40 +01:00 |
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Dolu1990
|
130ed6345c
|
boot
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2017-03-08 22:17:48 +01:00 |