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VexRiscv
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639 Commits

Author SHA1 Message Date
Charles Papon c01c256757 Revert "Merge branch 'master' into dev" 
This reverts commit b5374433a5, reversing
changes made to f01da9c73b.
 2020-01-29 15:20:13 +01:00
Charles Papon b5374433a5 Merge branch 'master' into dev 2020-01-29 12:50:41 +01:00
sebastien-riou badc38d645 Merge remote-tracking branch 'origin/master' into arty 2020-01-17 00:54:19 +01:00
sebastien-riou 1fb1e358bb fix makefile clean target 2020-01-17 00:49:35 +01:00
sebastien-riou 97b2838d18 Murax on Digilent Arty A7-35 2020-01-16 21:58:55 +01:00
sebastien-riou de9f704de2 better pin names in scala, bootloader without magic word 2020-01-13 21:58:08 +01:00
Charles Papon f01da9c73b CsrPlugin add printCsr 2020-01-13 20:44:55 +01:00
sebastien-riou b866dcb07f XIP on Murax improvements 2020-01-12 16:08:14 +01:00
Charles Papon 4c7025b964 Fix xtval when no exception and read_only 2020-01-06 20:07:23 +01:00
Charles Papon 2a06907902 fix compilation 2019-12-24 01:09:55 +01:00
Charles Papon 3b494e97cd Moved KeepAttribute to spinal.lib 2019-12-24 00:43:36 +01:00
Charles Papon 052c8dd602 Fix inWfi naming, fix regressions 2019-12-20 00:21:55 +01:00
Charles Papon 0702f97806 CsrPlugin add wfiOutput 2019-12-19 22:55:17 +01:00
Charles Papon e25dfb4fbf CsrPlugin now make SATP write rescheduling the next instruction 2019-12-09 22:23:07 +01:00
Charles Papon 744b040c70 Sync CFU progress 2019-11-29 11:50:00 +01:00
Charles Papon 7ae218704e CsrPlugin now implement a IWake interface 
DebugPlugin now wake the CPU if a halt is asked to flush the pipeline
 2019-11-19 18:36:53 +01:00
Charles Papon 6d0d70364c Add BranchPlugin.decodeBranchSrc2 for branch target configs 2019-11-08 14:01:53 +01:00
Charles Papon 4fe7fa56c7 GenCustomInterrupt demo now enabled vectored interrupt 2019-11-07 19:55:26 +01:00
Charles Papon bb405e705b Add UserInterruptPlugin 2019-11-07 19:52:45 +01:00
Charles Papon 8839f8a8e9 Fix DBus AXI bridges from writePending counter deadlock 2019-11-03 16:45:24 +01:00
Charles Papon 2bf6a536c9 Fix DBus AXI bridges from writePending counter deadlock 2019-11-03 16:44:09 +01:00
Charles Papon bd2787b562 RegFilePlugin project X0 against boot glitches if no x0Init but zeroBoot 2019-11-01 16:24:07 +01:00
Charles Papon bb9261773b Fix MulDiveIterative plugin when RSx have hazard in the execute stage 2019-10-23 00:02:08 +02:00
Charles Papon 67028cdb48 Add Mul16Plugin to regression tests 
Fix missing MulSimplePlugin in regressions tests
 2019-10-21 12:53:53 +02:00
Charles Papon 8091a872f3 Fix muldiv plugin for CPU configs without memory/writeback stages 2019-10-21 12:53:03 +02:00
Richard Petri 2d56c6738c Multiplication Plugin using 16-bit DSPs 2019-10-20 22:24:19 +02:00
Charles Papon b4c75d4898 Merge remote-tracking branch 'origin/dev' into dev 2019-10-11 00:25:37 +02:00
Charles Papon a2b49ae000 Fix CFU arbitration, add CFU decoder, CFU now redirect custom-0 with func3 2019-10-11 00:25:22 +02:00
Charles Papon 310c325eaa IBusCached add Keep attribut on the line loader to avoid Artix7 block ram merge, but do not seem to have effect 2019-10-11 00:24:21 +02:00
Charles Papon 711eed1e77 MulPlugin add withInputBuffer feature and now use RSx instead of SRCx 2019-10-11 00:23:29 +02:00
Charles Papon 3fc0a74102 Add Keep attribut on dBusCached relaxedMemoryTranslationRegister feature 2019-10-11 00:22:44 +02:00
Charles Papon 51d22d4a8c Merge remote-tracking branch 'origin/cfu' into dev 2019-10-10 15:00:43 +02:00
Charles Papon 5df56bea79 Allow getDrivingReg to properly see i$ decode.input(INSTRUCTION) register 
(used to inject instruction from the debug plugin)
 2019-10-03 00:20:33 +02:00
Charles Papon 49944643d2 Add regression for data cache without writeback stage, seem to pass tests, including linux ones 2019-09-23 15:20:51 +02:00
Charles Papon bf82829e9e Data cache can now be used without writeback stage 2019-09-23 15:20:20 +02:00
Charles Papon ace963b542 Hazard on memory stage do not need to know if that's bypassable if the memory stage is the last one 2019-09-21 14:13:28 +02:00
Charles Papon e1795e59d5 Enable RF bypass on MUL DIV with pipeline wihout writeback/memory stages 2019-09-21 13:00:54 +02:00
Charles Papon e8236dfebe Add MulSimplePlugin regressions 2019-09-21 12:49:46 +02:00
Sean Cross b8b053e706 muldiviterative: fix build for short pipelines 
Signed-off-by: Sean Cross <sean@xobs.io>
 2019-09-20 08:36:01 +08:00
Sean Cross fdc95debef dbuscached: fix build for short pipelines 
Signed-off-by: Sean Cross <sean@xobs.io>
 2019-09-20 08:35:49 +08:00
Sean Cross 0b79c637b6 mulsimpleplugin: fix build for short pipelines 
Signed-off-by: Sean Cross <sean@xobs.io>
 2019-09-20 08:35:23 +08:00
Charles Papon 6ed41f7361 Improve CSR FMax 2019-09-16 13:53:55 +02:00
Charles Papon d94cee13f0 Add dummy decoding, exception code/tval 
Add Cpu generation code
Add support for always ready rsp
 2019-09-05 19:06:28 +02:00
Charles Papon 5ac443b745 Manage cases where a rsp buffer is required 2019-09-05 10:41:45 +02:00
Dolu1990 6951f5b8e6 CfuPlugin addition 2019-09-05 10:41:45 +02:00
Mateusz Holenko 86f5af5ca9 Fix handling LiteX uart and timer. 2019-09-05 10:41:45 +02:00
Mateusz Holenko 8813e071bc Add `litex` target 
Use configuration from the `csr.h` file
generated dynamically when building a LiteX platform.
 2019-09-05 10:41:45 +02:00
Mateusz Holenko 64a2815544 Create makefile targets 
Allow to change build target without modifiying the sources.
In order to keep compatibilty `sim` target is built by default.
 2019-09-05 10:41:45 +02:00
Mateusz Holenko e76435c6c6 Allow to set custom DTB/OS_CALL addresses 
Setting those from command line during compilation allows
to create a custom setup without the need of modifying the
sources.
 2019-09-05 10:41:45 +02:00
Mateusz Holenko c8280a9a88 Allow to set custom RAM base address for emulator 
This is needed when loading the emulator to RAM
with an offset.
 2019-09-05 10:41:45 +02:00