Dolu1990
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f18696357f
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SpinalHDL 1.2.2
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2018-11-22 22:45:07 +01:00 |
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Dolu1990
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3e17461cc7
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Add optional XIP to Murax
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2018-09-16 11:00:56 +02:00 |
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Dolu1990
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0476de8066
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Move to SpinalHDL 1.2.0
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2018-09-16 10:16:43 +02:00 |
Dolu1990
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d7cba38ec2
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move to SpinalHDL 1.1.7, add more default value for plugins parameters
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2018-09-11 16:08:28 +02:00 |
Snoopy87
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304c8156a0
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Update version
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2018-08-24 06:51:10 +02:00 |
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Dolu1990
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5943ee727e
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Fill travis, DhrystoneBench is now a Unit test
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2018-05-28 09:02:01 +02:00 |
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Dolu1990
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35fbf177e2
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Update to SpinalHDL 1.1.6
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2018-05-16 12:12:09 +02:00 |
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Dolu1990
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2f8f4d5444
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SpinalHDL 1.1.5
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2018-03-13 15:45:56 +01:00 |
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Dolu1990
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53970dd284
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SpinalHDL 1.1.4
Now the CsrPlugin is waiting that the memory/writeback stages are empty before reading/writing things
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2018-03-05 14:34:59 +01:00 |
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Dolu1990
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3b3bbd48b9
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SpinalHDL 1.1.3 => Now Verilog rom are emited into separated bin files
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2018-01-20 18:29:33 +01:00 |
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Dolu1990
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9a89573942
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SpinalHDL 1.1.2
Add Murax setup with Mul Div Barriel
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2018-01-06 22:09:42 +01:00 |
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Dolu1990
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4ed19f2cc5
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SpinalHDL 1.1.1
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2017-12-30 03:36:57 +01:00 |
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Dolu1990
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0d39e38906
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SpinalHDL 1.1.0
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2017-12-28 13:49:39 +01:00 |
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Dolu1990
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3a913f0789
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SpinalHDL 1.0.5
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2017-12-22 23:18:34 +01:00 |
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Dolu1990
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7f2b2181c1
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SpinalHDL 1.0.3
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2017-12-19 21:21:16 +01:00 |
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Dolu1990
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37849b7a66
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Spinal 1.0.2 sim update
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2017-12-19 00:40:52 +01:00 |
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Dolu1990
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15463a6276
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spinalhdl 1.0.1
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2017-12-17 19:36:18 +01:00 |
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Dolu1990
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2259c9cb0f
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Add SpinalHDL sim (1.0.0)
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2017-12-14 00:57:12 +01:00 |
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Dolu1990
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f10dabd253
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SpinalHDL 0.11.5 update
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2017-12-05 15:58:05 +01:00 |
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Dolu1990
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e1b86ea511
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SpinalHDL 0.11.4 update
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2017-12-01 11:19:23 +01:00 |
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Dolu1990
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ce6fd6d0aa
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Add VexRiscvAxi4 demo
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2017-11-20 23:57:37 +01:00 |
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Dolu1990
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9f9ec823b8
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SpinalHDL 0.11.2
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2017-11-15 17:57:08 +01:00 |
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Dolu1990
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6c3fed3505
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SpinalHDL 0.11.1
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2017-11-15 16:44:42 +01:00 |
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Dolu1990
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ba42f71813
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pass VexRiscv regressions
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2017-10-30 14:29:25 +01:00 |
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Charles Papon
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a37494f27f
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Set sbt organization to com.github.spinalhdl
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2017-08-01 20:43:15 +02:00 |
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Charles Papon
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823ac353ff
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Add Murax SoC (very light, work on ice40)
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2017-07-28 21:25:49 +02:00 |
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Charles Papon
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a94343b98a
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Update to SpinalHDL 0.10.14
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2017-06-17 15:15:19 +02:00 |
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Charles Papon
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11a63491bd
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Add YAML feature to store CPU info
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2017-06-09 16:06:18 +02:00 |
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Charles Papon
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6b62d8da52
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VexRiscv in Briey SoC is working on FPGA (including jtag debugging)
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2017-05-29 21:17:14 +02:00 |
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Dolu1990
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fcb70a333f
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WIP
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2017-03-11 00:34:49 +01:00 |
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Dolu1990
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130ed6345c
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boot
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2017-03-08 22:17:48 +01:00 |