172add8dfc
Merge pull request #240 from antmicro/jboc/lpddr4
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lpddr4: add a local README with a summary of the code
2021-04-01 18:54:42 +02:00
478157560f
Merge pull request #241 from antmicro/jboc/lpddr4-init-fix
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Fix Python header generation for LPDDR4
2021-04-01 18:53:38 +02:00
7028944acd
lpddr4: add missing copyright comments
2021-04-01 10:07:02 +02:00
c12e832bcb
init: fix python header generation
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With the previous code lines included python variable names instead of integers, e.g.
("ZQ Calibration start", MPC.ZQC_START, SpecialCmd.MPC, dfii_command_we|dfii_command_cs, 200)
which failed as these names were not being imported.
2021-03-31 15:58:43 +02:00
13db84ceb5
lpddr4: add a local README with a summary of the code
2021-03-31 12:51:34 +02:00
996d0add26
Merge pull request #224 from antmicro/jboc/lpddr4
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Add LPDDR4 PHY
2021-03-31 09:35:06 +02:00
f5e7c39776
Merge pull request #238 from antmicro/jboc/refresh-all-banks
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core/refresher: use A10=1 for an all-banks REF
2021-03-31 08:50:25 +02:00
df2a06584b
Merge pull request #237 from antmicro/jboc/dfii-bankbits
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core: use wider DFI address/bank if PHY requires it
2021-03-31 08:48:32 +02:00
04334ae141
phy/s7ddrphy/usddrphy: Use explicit sys clock domain on ClockSignal/ResetSignal.
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Improve readability.
2021-03-30 08:51:44 +02:00
5cd192a708
bench: Remove soc_sdram import (No longer useful and deprecated).
2021-03-30 08:49:54 +02:00
06b30979dd
lpddr4/s7phy: add with_odelay parameter and Artix/Kintex/Virtex variants
2021-03-25 15:31:58 +01:00
e07198ac57
lpddr4/utils: simplify ConstBitSlip
2021-03-25 15:31:58 +01:00
e860d86f3f
lpddr4/phy: make redundant cmd overlaps checks optional (and disabled by default)
2021-03-25 15:31:58 +01:00
f282d809d1
lpddr4: remove old fixme comments
2021-03-25 15:31:58 +01:00
a64cb58753
core/refresher: use A10=1 for all banks REF
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This is needed because newer DRAMs like LPDDR4 or DDR5 have
separate commands for per-bank refresh and all banks refresh.
Other DRAM types ignore address for REF commands.
2021-03-25 15:31:58 +01:00
a21b70e061
init: revert bitslips changed to 16 for phys other than S7LPDDR4PHY
2021-03-25 15:31:58 +01:00
f3a0a7d038
lpddr4/s7phy: remove OE delay CSRs, use fixed, tested values
2021-03-25 15:31:58 +01:00
ba57791c1d
lpddr4/s7phy: extend time of holding output enable on tristate lines
2021-03-25 15:31:58 +01:00
58235f478e
lpddr4/init: increase CA/DQ Vref to 30.4% (yields better results)
2021-03-25 15:31:58 +01:00
693695f067
lpddr4/init: initialize all More Registers (even if setting defaults)
2021-03-25 15:31:58 +01:00
0ecb1340f5
lpddr4/test: fixes: use 2tCK write preamble, update read latency
2021-03-25 15:31:05 +01:00
5c6796b92a
lpddr4: change MRW command encoding to avoid changing BIOS code
2021-03-25 15:30:48 +01:00
f1a40cef2f
core: use wider DFI address/bank if PHY requires it
2021-03-25 15:29:32 +01:00
eb1d900c24
lpddr4: S7PHY related fixes, MRR command, runtime configurable WRITE/MASKED-WRITE
2021-03-25 15:29:17 +01:00
052dc19246
lpddr4: improve documentation
2021-03-25 15:21:01 +01:00
1b65e858b3
lpddr4/utils: rework `once` helper function to be more generic
2021-03-25 15:21:01 +01:00
4473335954
lpddr4/commands: replace MPC dict with an enum with docstring
2021-03-25 15:19:16 +01:00
7f19e92c75
ci: add dependencies required for Verilator-based tests
2021-03-25 15:19:16 +01:00
4415a3eaf5
lpddr4: improve simulation and Verilator tests runner
2021-03-25 15:19:16 +01:00
4a5feb9e11
lpddr4/s7phy: improve to use the new DoubleRateLPDDR4PHY
2021-03-25 15:19:16 +01:00
2ab763ac5e
lpddr4: add double-rate PHY, clean up and improve PHY implementation
2021-03-25 15:19:16 +01:00
183f1643aa
lpddr4: add support for MASKED-WRITE
2021-03-25 15:19:16 +01:00
4b78fc99e8
lpddr4/sim: create LPDDR4 simulator and Verilator target
2021-03-25 15:19:16 +01:00
05ed238829
lpddr4: split implementation into multiple files in separate directory
2021-03-25 15:19:16 +01:00
ee9c2b4cf7
lpddr4: implement ZQC through MPC and include it in init sequence
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We do not yet support ZQC during operation (after init sequence)
as LPDDR4 requires 2-stage ZQC (start+latch) and 1us in between,
which requires modifying Refresher (ZQCExecutor) in LiteDRAM.
2021-03-25 15:19:16 +01:00
055e2dc597
lpddr4: add initial PHY for Series7
2021-03-25 15:19:16 +01:00
4d9106847f
init: add LPDDR4 initialization
2021-03-25 15:19:16 +01:00
788b3f6d02
modules: modules: add LPDDR4 module
2021-03-25 15:19:16 +01:00
6943a1a4a5
lpddr4: initial PHY logic and simulation tests
2021-03-25 15:19:08 +01:00
f0de06091e
core/refresher: use A10=1 for all banks REF
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This is needed because newer DRAMs like LPDDR4 or DDR5 have
separate commands for per-bank refresh and all banks refresh.
Other DRAM types ignore address for REF commands.
2021-03-24 10:31:06 +01:00
de12e62ac5
core: use wider DFI address/bank if PHY requires it
2021-03-23 12:41:31 +01:00
7d522cefc3
modules.py: Add MT41J256M8 (Passes mem_test on HW @ sys4x=500MHz, vexriscv, marble board)
2021-03-22 13:55:39 -07:00
f17037fdb2
bench/common: Cleanup, Increase sys_clk measure time to 5s.
2021-03-12 14:29:43 +01:00
3f9759b83b
bench/xcu1525: Update build directories.
2021-03-12 10:59:06 +01:00
df5f555842
bench: Update with recent changes.
2021-03-12 10:25:11 +01:00
e3c2ab0757
phy/usddrphy: Add missing i_RST on DQS's ODELAYE3.
2021-03-04 14:44:07 +01:00
06411b2a72
frontend/dma: Modify CSR interface to be similar to LiteX's DMA (start becomes a enable), also add offset CSR to keep track of current status.
2021-03-04 11:58:33 +01:00
e9d5128811
frontend/dma: Add default CSR values to add_csr. (Allow initializing DMA after reset without software intervention).
2021-03-03 19:42:40 +01:00
25b64c3374
phy/usddrphy: Avoid separate ODELAYE3 by avoiding software reset on DQS's ODELAYE3.
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The fabric is now maintaining an increment counter for each DQS's ODELAY and software
use it to revert total increments to 0 (equivalent to a reset).
Avoiding the separate ODELAYE3 simplifies design constraints since it was often placed
far from the DRAM pads and thus requiring a LOC constraint to avoid timing violations.
The software has to use the following sdram_write_leveling_rst_delay function:
static void sdram_write_leveling_rst_delay(int module) {
/* Select module */
ddrphy_dly_sel_write(1 << module);
/* Reset DQ delay */
ddrphy_wdly_dq_rst_write(1);
/* Reset DQS delay */
while (ddrphy_wdly_dqs_inc_count_read() != 0) {
ddrphy_wdly_dqs_inc_write(1);
cdelay(100);
}
/* Un-select module */
ddrphy_dly_sel_write(0);
}
2021-03-03 11:29:58 +01:00
541e2f1c57
litedram_gen: Avoid multi-lines on user_port.
2021-03-02 10:54:20 +01:00
enjoy-digital
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