Florent Kermarrec
|
d9da7c54ee
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phy/s7ddrphy: compute phy settings automatically (based on tck) and add DDR3-1066/1333/1600 support.
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2018-06-28 18:50:56 +02:00 |
Florent Kermarrec
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ba16ebfb22
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phy: add common Series7 PHY (Artix7, Kintex7 & Virtex7) with or without ODELAY. Keep backward compatibility on imports.
|
2018-06-12 15:36:39 +02:00 |
Florent Kermarrec
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2bd7707e67
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modules: add MT18KSF1G72HZ_1G6
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2018-06-12 09:54:38 +02:00 |
|
6b0d5ceeae
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Prevent spurious precharge all commands caused by leaving A10 asserted during precharge
|
2018-05-03 14:29:39 -04:00 |
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d0fcfb172f
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Auto-precharge now only fires when it needs to
|
2018-05-03 03:34:21 -04:00 |
Florent Kermarrec
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c23814961d
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phy/kusddrphy: follow more Xilinx recommandations
|
2018-03-13 22:33:33 +01:00 |
Florent Kermarrec
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45da365b7f
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phy/kusddrphy: add odelaye3 on all outputs (to have identical delays on all outputs before software dq/dqs delay configuration)
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2018-03-09 20:46:19 +01:00 |
Florent Kermarrec
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f905fda8ff
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phy/kusddrphy: use IOBUFDSE3 on dqs to be able to apply ODT=RTT_40 constraint
|
2018-03-09 13:01:48 +01:00 |
Florent Kermarrec
|
e6a99d9cbc
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phy/kusddrphy: revert dqs preamble/postamble since not working for continous transfer, will need a proper implementation
|
2018-03-08 13:15:28 +01:00 |
Florent Kermarrec
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66d99a3e36
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phy/kusddrphy: add dqs preamble/postamble instead of always toggling on oe_dqs
|
2018-03-08 10:44:48 +01:00 |
Florent Kermarrec
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da4651ff19
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phy/kusddrphy: add comment
|
2018-03-08 08:33:31 +01:00 |
Florent Kermarrec
|
0d7a7a99e0
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phy/kusddrphy: store dqs taps init value in csr at startup
|
2018-03-07 23:32:39 +01:00 |
Florent Kermarrec
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b885f582f3
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phy/kusddrphy: operate delays in time mode (to be able to specify 500ps delay on dqs) and add workaround to allow software to get number of taps for 500ps at init.
|
2018-03-07 16:23:27 +01:00 |
Florent Kermarrec
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459060ede3
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phy/kusddrphy: add en_vtc control
|
2018-03-07 12:14:16 +01:00 |
Florent Kermarrec
|
48bc3cb15d
|
README: add migen dependency
|
2018-03-01 10:43:08 +01:00 |
Florent Kermarrec
|
697f46a97f
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replace litex.gen imports with migen imports
|
2018-02-23 13:39:23 +01:00 |
Florent Kermarrec
|
bd43fd605c
|
bump to 0.2.dev
|
2018-02-23 13:39:06 +01:00 |
Florent Kermarrec
|
45a948d42a
|
uniformize litex cores
|
2018-02-22 10:10:54 +01:00 |
Florent Kermarrec
|
58389534e6
|
modules: add MT47H64M16
|
2018-02-06 19:19:14 +01:00 |
Florent Kermarrec
|
57c63c1eab
|
phy/a7ddrphy: make reset_n optional
|
2018-02-06 14:48:52 +01:00 |
Florent Kermarrec
|
ec9ad2fc39
|
frontend/dma: add description of fifo_buffered parameter
|
2018-01-31 09:32:21 +01:00 |
Tim Ansell
|
13d41f67ab
|
Merge pull request #9 from felixheld/indentation-fixes
Fix all remaining indentation issues in python code
|
2018-01-13 13:38:02 +11:00 |
Felix Held
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72b1b109b7
|
Fix all remaining indentation issues in python code
I ran a script that shouldn't have missed any tab in the python source files.
|
2018-01-13 13:22:08 +11:00 |
Florent Kermarrec
|
a09b7a05b8
|
phy/kusddrphy: typo
|
2017-12-08 16:10:10 +01:00 |
Florent Kermarrec
|
010a6a2b91
|
phy/kusddrphy: use initial delay value on dqs instead of shifted sys4x clock
|
2017-12-08 15:52:52 +01:00 |
Florent Kermarrec
|
26d60fa781
|
doc: add simple architecture diagram
|
2017-11-13 18:49:35 +01:00 |
Florent Kermarrec
|
eb6010d784
|
phy/kusddrphy: use locally inverted clk_b on iserdese3
|
2017-11-10 00:46:20 +01:00 |
Florent Kermarrec
|
38f1c268e9
|
phy/kusddrphy: reset bitslip on wdly_dq_rst instead of rdly_dq_rst
|
2017-11-08 21:52:56 +01:00 |
Florent Kermarrec
|
f31f8a03ff
|
modules: add MT46H32M32
|
2017-07-25 10:34:03 +02:00 |
Florent Kermarrec
|
47755e5637
|
phy/kusddrphy: fix typo on oserdese3/odatain (no functional impact)
|
2017-07-12 08:43:14 +02:00 |
Florent Kermarrec
|
f251800fb6
|
phy/kusddrphy: use similar bitslip interface than kintex7
|
2017-07-10 15:50:47 +02:00 |
Florent Kermarrec
|
40a8504dd6
|
phy/kusddrphy: use specific sys4x_dqs clock since we can't ensure initial delay between dq/dqs using odelaye3 on ultrascale...
tap delay can vary from 2.5 to 15ps across PVT
|
2017-07-10 14:39:54 +02:00 |
Florent Kermarrec
|
5977a6fca0
|
phy/kusddrphy: remove comment on idelaye3 initial delay since fully covered by software
|
2017-07-10 13:59:24 +02:00 |
Florent Kermarrec
|
86b0cc0a56
|
frontend/bist: restrict lfsr to 32 bit allow bist with large ddram
msbs data are then filled with zeros, but we should fix lfsr generation to avoid this
|
2017-07-10 12:02:13 +02:00 |
Florent Kermarrec
|
33ca8d604e
|
frontend/bist: use bytes for base and length parameters
|
2017-07-10 10:02:41 +02:00 |
Florent Kermarrec
|
7b31005bc4
|
phy/kusddrphy: fix input bit ordering, working :)
|
2017-07-08 18:46:53 +02:00 |
Florent Kermarrec
|
99fe71d622
|
phy/kusddrphy: revert delays control and add comments for initial delays values
|
2017-07-08 10:54:02 +02:00 |
Florent Kermarrec
|
aad2f92b33
|
phy/kusddrphy: IOBUF incorrect behaviour fixed by upgrading vivado to 2017.2...
|
2017-07-08 10:13:58 +02:00 |
Florent Kermarrec
|
a72ba87f3e
|
phy/kusddrphy: use fixed delays for initial board test, identify strange behaviour of IOBUF...
|
2017-07-08 09:41:08 +02:00 |
Florent Kermarrec
|
7ea734381e
|
phy/kusddrphy: phy has been simulated, remove from TODO
|
2017-07-07 09:03:54 +02:00 |
Florent Kermarrec
|
b21a9d8e18
|
phy/kusddrphy: add phy reset (just to be sure primitives are correctly reseted, will be removed if not needed)
|
2017-07-07 09:02:58 +02:00 |
Florent Kermarrec
|
fa3535f7c0
|
phy/kusddrphy: verify latencies with simulation
|
2017-07-06 19:21:38 +02:00 |
Florent Kermarrec
|
abf028e0be
|
global: reset_less optimizations
|
2017-07-01 11:18:05 +02:00 |
Florent Kermarrec
|
67df00bcac
|
frontend/bist: use new reset_less attribute where possible
|
2017-06-29 11:20:08 +02:00 |
Florent Kermarrec
|
c8713bfb48
|
litedram/frontend/bist: cleanup and add ticks counters to measure performance with hardware
|
2017-06-29 10:41:34 +02:00 |
Florent Kermarrec
|
6091c6de60
|
frontend: remove fifo, too complex to get working and too many corner cases (data stuck in pipeline, ...)
|
2017-06-28 12:30:59 +02:00 |
Florent Kermarrec
|
369e9308b9
|
frontend/fifo: simplify and only keep raw layout
|
2017-06-27 17:24:32 +02:00 |
Florent Kermarrec
|
883e97101a
|
common: add id to ports
|
2017-06-27 15:06:12 +02:00 |
Florent Kermarrec
|
9ce2f67bb1
|
frontend: add dram fifo (untested)
|
2017-06-23 22:00:49 +02:00 |
Florent Kermarrec
|
bab0150c87
|
README: consistency between projects
|
2017-06-22 16:57:14 +02:00 |