e662fadf8a
test/test_init: Update.
2022-05-10 10:38:55 +02:00
18d25d84c3
Update test/reference/*_init.h
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Signed-off-by: Ryszard Różak <rrozak@antmicro.com>
2022-03-30 13:42:47 +02:00
095180be6a
frontend/AXI: Add optional Read-Modify-Write mode for cases where w.strb is not available on the DRAM side (ex when ECC is enabled).
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When enabled, partial writes are automatically detected and a Read-Modify-Write access is
done. Before doing a RMW access, pending accesses are terminated and incoming accesses are
stalled until RMW access is done.
Enable with_read_modify_write in test_axi.
2022-02-28 18:45:46 +01:00
81ae73b74a
test/test_axi: Exercise w.strb through randomness (as we are doing for data).
2022-02-28 18:35:39 +01:00
2d47363f46
test/benchmark: Switch from soc_sdram (deprecated) to soc_core.
2022-01-07 18:37:13 +01:00
cea9d00d20
Merge pull request #270 from antmicro/jboc/lpddr5-rebase
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LPDDR5 support
2021-11-01 22:18:38 +01:00
3b47170a0c
Merge pull request #273 from antmicro/rpc-dram-support
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Add RPC DRAM support
2021-11-01 21:52:36 +01:00
a8afbe8b08
test/test_refresh: Update.
2021-11-01 15:33:21 +01:00
50ba27eb4c
lpddr5: tests: add additional initial tCK delay for bitslip
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Signed-off-by: Alessandro Comodi <acomodi@antmicro.com>
2021-10-26 12:22:30 +02:00
ab130e170a
lpddr5: add write leveling support
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Signed-off-by: Alessandro Comodi <acomodi@antmicro.com>
2021-10-26 12:22:30 +02:00
43aef6255e
phy/lpddr5: add Verilator tests
2021-10-26 12:22:30 +02:00
2989963b9c
phy: move regex pattern for parsing SimLogger logs to SimLogger class
2021-10-26 12:22:30 +02:00
abc77f367c
lpddr5: wck sync: fix syncing and adjusted unit tests
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Signed-off-by: Alessandro Comodi <acomodi@antmicro.com>
2021-10-26 12:22:30 +02:00
c4273146c1
lpddr5: wck sync: adapt tests as now wck sync is required
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Signed-off-by: Alessandro Comodi <acomodi@antmicro.com>
2021-10-26 12:22:30 +02:00
8c10f1405b
phy/lpddr5: delay WCK sync FSM transition by 1 cycle
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With fixed serialization logic WCK sync can be now started later
which avoids the need for special logic when tWCKENL=0.
2021-10-26 12:22:30 +02:00
32a56ffe28
phy/lpddr5: fix command serialization
2021-10-26 12:22:30 +02:00
4e974738d1
phy/lpddr5: fix column address encoding/decoding
2021-10-26 12:22:30 +02:00
914d018cf8
phy/sim_utils: support low wait times (0/1) in PulseTiming
2021-10-26 12:22:30 +02:00
2671508a11
phy/lpddr5: add simulation SoC
2021-10-26 12:22:30 +02:00
7cdf0e11ca
phy/lpddr5: add unit tests
2021-10-26 12:22:30 +02:00
136be83749
frontend/fifo: Revisit DRAM state to avoid deadlock situations when port_data_width != port_address_width.
2021-10-06 18:05:48 +02:00
3d3bf623aa
frontend/fifo: Simplify, fix corner cases.
2021-09-23 23:22:51 +02:00
dd24073633
test/test_fifo: Use 4 x DRAM data-width in Bypass mode to use Pre/Post-Converter.
2021-09-23 18:57:00 +02:00
2d4a47f260
frontend/fifo: Add initial optional/automatic Bypass implementation to LiteDRAMFIFO.
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Bypass will provide lower latency and configurable data-width.
2021-09-21 19:23:36 +02:00
d95212bf0b
test: check converters at higher data width ratios
2021-09-01 14:59:05 +02:00
89af25a697
phy/utils: DFI rate converter for creating PHY wrappers at slower clocks
2021-08-04 12:30:56 +02:00
43036c9576
test: update *_init.h reference
2021-08-04 12:30:56 +02:00
2200bd43a5
test/reference: update headers to include SDRAM_PHY_DFI_DATABITS
2021-08-04 12:30:56 +02:00
91cae335e5
init: add parentheses around #define with an expression
2021-08-04 12:30:56 +02:00
a3aa4907f1
phy/lpddr4/simsoc: Change cpu_variant to lite and revert commented test_lpddr4_sim_x2rate_no_cache.
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(see #255 ).
2021-07-02 09:24:11 +02:00
317072a198
litedram_gen: Add initial SDRAM support (with ULX3S example).
2021-07-02 09:01:31 +02:00
34fbe01a78
test/phy_common: make chunk size in PadsHistory summary configurable
2021-06-22 11:41:44 +02:00
eb6e7a1514
test/lpddr4: move dfi_data_to_dq to common code
2021-06-22 11:41:44 +02:00
fcda73a175
test/phy_common: simplify calls to run_simulation
2021-06-22 11:41:44 +02:00
da769094fd
phy/lpddr4: fix edge case error with CommandsPipeline ignoring a command
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Command was being ignored when it occurred on the last phase and
the next command would invalidate the first phase. Now it is fixed
and a regression test is included. A fix in ConstBitSlip has been added
due to wrong Verilog being generated with cycles=1, register=False.
2021-06-22 11:40:51 +02:00
baf9c07858
phy/utils: improve ConstBitSlip:
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* optional register=False to decrease latency by 1 cycle
* require explicit `cycles` as it influences latency (min_cycles
still can be used)
* add unit tests
2021-06-21 14:43:49 +02:00
4a96be86c0
test/lpddr4: move run_simulation wrapper to phy_common.py
2021-06-21 14:43:49 +02:00
1543fa4ace
phy/lpddr4: extract common test helpers for use when testing other PHYs
2021-06-21 14:43:49 +02:00
47e8a59511
phy/lpddr4: extract SimulationPads and use it as a base class
2021-06-21 14:43:49 +02:00
8e563239f9
phy/lpddr4: extract common utilities
2021-06-21 13:22:15 +02:00
377d6fac6c
test/test_lpddr4: Disable failing test.
2021-06-08 15:07:53 +02:00
2fcc6fe552
test/test_ecc: Update.
2021-06-08 15:07:39 +02:00
dc6cb89737
also remove 'static' from cdelay() declarations in test suite
2021-05-26 12:09:26 -04:00
b8cd26fa52
test/refefence: Update.
2021-05-18 11:26:40 +02:00
0877a81b4b
test/test_init: Add simple way to update references.
2021-05-18 11:26:19 +02:00
63358ee666
test/reference: Update.
2021-04-28 18:21:27 +02:00
886f60d32c
test/reference: Update.
2021-04-23 11:26:30 +02:00
7028944acd
lpddr4: add missing copyright comments
2021-04-01 10:07:02 +02:00
e860d86f3f
lpddr4/phy: make redundant cmd overlaps checks optional (and disabled by default)
2021-03-25 15:31:58 +01:00
0ecb1340f5
lpddr4/test: fixes: use 2tCK write preamble, update read latency
2021-03-25 15:31:05 +01:00
Florent Kermarrec
Ryszard Różak
Alessandro Comodi
Jędrzej Boczar
Gabriel Somlo