26 commits

Author	SHA1	Message	Date
Florent Kermarrec	2bdeda021b	move standalone core generation to litedram package and make it usable externally ... When LiteDRAM is installed, standalone core can now be generated with "litedram_gen config.yml"	2019-08-28 07:19:30 +02:00
Florent Kermarrec	0dde125740	examples/litedram_gen: fix #!/usr/bin/env python3 location	2019-08-28 07:09:58 +02:00
Florent Kermarrec	602ff8be81	examples: switch to YAML config files	2019-08-28 07:08:10 +02:00
Florent Kermarrec	f018c9e268	add CONTRIBUTORS file and add copyright header to all files.	2019-06-23 23:59:10 +02:00
Gabriel L. Somlo	65451f426a	examples/litedram_gen: allow direct access to CSR (I/O) registers ... Signed-off-by: Gabriel Somlo <gsomlo@gmail.com> [florent@enjoy-digital.fr: use add_csr_master, fix csr_port.dat_r typo]	2019-05-16 15:05:30 -04:00
Florent Kermarrec	b93412bbdc	examples: remove verilog simulation ... Simulation was here just to show how to do system level simulation adn required external component to work (stadalone init).	2019-05-10 13:05:48 +02:00
Florent Kermarrec	a7e46bb25c	example/litedram_gen: reserve_nmi_interrupt no longer exists	2019-05-10 12:43:23 +02:00
Florent Kermarrec	c4161cfbfe	examples: update sim	2019-03-15 20:16:42 +01:00
Florent Kermarrec	640194a5c9	examples: add nexys4ddr_config	2019-02-21 23:32:45 +01:00
Florent Kermarrec	0ac1af367a	examples/litedram_gen: add DDR2 support	2019-02-21 23:32:23 +01:00
Florent Kermarrec	f4184ec37a	example/litedram_gen: update, add descriptions of config parameters	2019-02-21 23:19:52 +01:00
Florent Kermarrec	bc6a3f220a	examples/sim/sim/py: remove apb interface	2018-11-17 09:30:58 +01:00
Florent Kermarrec	e7e4bc527f	examples/sim: add ddr3 micron model	2018-11-17 09:20:34 +01:00
Florent Kermarrec	f219693635	examples: add simulation	2018-11-17 09:19:52 +01:00
Florent Kermarrec	f11506accd	examples/litedram_gen: cleanup pins definition	2018-10-15 09:38:34 +02:00
Florent Kermarrec	0f46dc4ab7	modules: add DDR3-800 timings for MT41J128M16 and use it on arty example	2018-10-01 11:59:54 +02:00
Florent Kermarrec	426ae23d2a	examples/litedram_gen: add sdram_module_speedgrade parameter	2018-10-01 11:48:15 +02:00
Florent Kermarrec	30c32f557c	example/litedram_gen: simplify clocking with new S7PLL module, a lot easier :)	2018-09-25 10:40:24 +02:00
Florent Kermarrec	37f1decfb2	multirank: one cs_n/cke/odt/clk per rank	2018-09-09 14:32:15 +02:00
Florent Kermarrec	8ddc6c735d	drive odt of all ranks, fixes and test non regression with 1 rank	2018-09-09 01:52:24 +02:00
Florent Kermarrec	cc481be81f	examples: add sdram_rank_nb and user_ports_id_width	2018-09-07 17:55:46 +02:00
Florent Kermarrec	1652ab95c8	examples/litedram_gen: fix address width of axi ports (addressing in bytes not words)	2018-09-05 09:13:47 +02:00
Florent Kermarrec	1e64b7f492	examples/litedram_gen: expose resp signals to user	2018-09-05 08:51:27 +02:00
Florent Kermarrec	de69867995	examples/litedram_gen: expose last signals to user	2018-09-05 08:32:49 +02:00
Florent Kermarrec	e8bd782999	examples/litedram_gen: expose burst signals to user	2018-09-05 08:31:57 +02:00
Florent Kermarrec	5e4dca9a7b	add examples with standalone cores for arty and genesys2	2018-08-31 23:20:47 +02:00