83d70a3eb9
phy/s7ddrphy: also add bitslip on dqs.
2020-10-08 18:17:47 +02:00
0ac23fde52
phy/s7ddrphy: increase write_latency by 1 (now possible with previous BitSlip chantges).
2020-10-08 18:08:36 +02:00
3fddff3a11
common/BitSlip: shift output by one bit (allow 1 cycle latency on writes), set reset value to cycles*dw-1.
2020-10-08 17:37:24 +02:00
732df04413
common/Bitslip: add assert on cycles.
2020-10-08 17:16:21 +02:00
6e8d37c873
phy/s7ddrphy: replace dm/dq delays with BitSlip.
2020-10-08 17:15:22 +02:00
c16628531a
common/BitSlip: allow passing i/o signals as parameters.
2020-10-08 16:56:22 +02:00
fcd1b2ca2b
phy/s7ddrphy: reduce write_latency on controller by 1 sys_clk (to allow BitSlip).
2020-10-08 16:23:06 +02:00
b24943e691
bench/genesys2: add litescope on ddrphy.dfi.
2020-10-08 16:21:02 +02:00
e5f4f828ad
phy/s7ddrphy: fix dynamic rd/wrphase and dq/dqs_oe_delay for nphases=2.
2020-10-07 18:54:43 +02:00
b16e9bfd5c
phy/s7/usddrphy: cleanup/uniformize DQ path.
2020-10-02 12:43:02 +02:00
39178ce460
test: add minimal OSERDESE2/OSERDESE3 simulations to check Data/Tristate latencies.
2020-10-02 12:30:19 +02:00
329c9904f7
common/DQSPattern: add transmission order, minor simplification on USDDRPHY.
2020-10-02 12:26:57 +02:00
16480d9aed
phy/s7ddrphy: adjust dqs/dq tristate latency.
...
OSERDESE2 has a latency of 2 sys_clk.
2020-10-02 12:15:32 +02:00
6a23bd623b
phy/ecp5/s7/usddrphy: simplify dq/dqs tristate using TappedDelayLine.
2020-10-02 09:37:32 +02:00
e3461704b5
phy/ecp5/s7/usddrphy: simplify control path using TappedDelayLine.
2020-10-01 18:30:17 +02:00
d12caf1e0c
common: add TappedDelayLine to simplify delays on control signals.
2020-10-01 18:29:35 +02:00
a5a4a422dd
phy/core: move rd/wrcmdphase and computation to Multiplexer.
...
rd/wrcmdphases are always computated as (rd/wrphase-1)%nphases so it's not useful
to expose them as PhySettings. rd/wrcmdphases are now directly computated in
Multiplexer and static/dynamic rd/wrphases are supported.
2020-10-01 11:26:04 +02:00
f8ee596464
test/reference: update.
2020-09-30 19:49:38 +02:00
c8f1e80215
phy/s7ddrphy: handle cmd_latency properly (add it to rd/wrphase).
2020-09-30 19:45:23 +02:00
b1c26d996f
phy/s7ddrphy: handle cmd_latency properly (add it to rd/wrphase).
2020-09-30 19:40:55 +02:00
05ed5bf59d
phy/ecp5ddrphy: simplify using new get_sys_phase.
2020-09-30 19:39:10 +02:00
207b8f48bb
common: simplify/rename get_sys_phase (cmd_phase is always -1 can be calculated on phys).
2020-09-30 19:38:43 +02:00
a611778e3d
litedram/init/get_sdram_phy_c_header: add CL/CWL defines.
2020-09-30 19:19:31 +02:00
6d063b196c
test/reference: update.
2020-09-30 18:06:48 +02:00
18e8f5c565
phy/usddrphy: add dynamic read/write phase support.
2020-09-30 17:13:55 +02:00
afe29d4231
phy/s7ddrphy: add dynamic read/write phase support.
2020-09-30 17:13:41 +02:00
a67aed2a02
init/get_sdram_phy_c_header: add support for dynamic write/read phases.
2020-09-30 17:07:34 +02:00
c4d7083677
test/reference: update.
2020-09-30 13:29:39 +02:00
d06e2dda23
phy/usddrphy: simplify dq_bitslip.o mapping.
2020-09-30 11:41:43 +02:00
6b0591920b
phy/usddrphy: simplify commands.
2020-09-30 11:39:07 +02:00
1d756cb209
phy/usddrphy: simplify OSERDESE3/ISERDESE3 data mapping.
2020-09-30 10:44:41 +02:00
5d41cce080
phy/gensdrphy: simplify commands and add dm support.
2020-09-30 10:39:36 +02:00
b772bb54a7
phy/ecp5ddrphy: simplify commands and ODDR/IDDR data mapping.
2020-09-30 09:52:39 +02:00
db8eaff086
phy/ecp5ddrphy: fix regression after DQS/DM changes.
2020-09-30 09:11:39 +02:00
c17bf3f5a1
phy/s7ddrphy: simplify commands (avoid duplication between address/banks/controls).
2020-09-30 08:04:45 +02:00
7f347af1ed
phy/s7ddrphy: simplify ISERDESE2/OSERDESE2 data mapping using for loops.
2020-09-30 07:33:52 +02:00
68e9a02a55
litedram/common: add cl/cwl values for DDR4 data rates from 1333MT/s to 2666MT/s.
2020-09-29 19:46:39 +02:00
c2d1cf358b
phy/ecp5/s7/usddrphy: separate DQS/DM to improve readability.
2020-09-29 19:23:34 +02:00
5aaffb7c16
phy/s7ddrphy: remove dqs_i/dqs_i_delayed (no longer used).
2020-09-29 19:00:25 +02:00
e69dbd2d91
bench: add DDR3 Mode Register settings generator.
...
Useful to change timing/electrical settings dynamically and bringup/debug DDR3 on new hardware.
2020-09-24 17:51:22 +02:00
7ccb7d8f16
test/reference: update.
2020-09-24 15:03:35 +02:00
5257197475
bench: add DDR4 Mode Register settings generator.
...
Useful to change timing/electrical settings dynamically and bringup/debug DDR4 on new hardware.
2020-09-24 14:57:14 +02:00
db54e325c8
phy/usddrphy: reduce BitSlip cycles to 1 sys_clk.
...
Increasing it to 2 hasn't been useful.
2020-09-24 13:36:02 +02:00
06544c6547
bench: uniformize targets with 125MHz clock and Etherbone.
2020-09-24 13:03:07 +02:00
0279b770ee
phy/s7ddrphy: avoid cdly CSRs when no odelay capability.
2020-09-22 10:58:14 +02:00
6fc6174c38
bench/genesys2: expose uart parameter.
2020-09-17 08:22:17 +02:00
8525a27762
test/reference: update.
2020-09-15 20:00:55 +02:00
8d39ac6dd1
phy/s7ddrphy: remove interface_type parameter and ISERDESE2's MEMORY_MODE support.
...
Supporting MEMORY_MODE add complexity to the codebase and this mode is not used by anyone.
It has been experimented on NeTV2 to solves instability at low temperature but hasn't improved
the behaviour.
2020-09-15 19:55:58 +02:00
c3b4b0d338
phy/s7ddrphy: reduce BitSlip's cycles to 1 (seems to be enough for all cases).
2020-09-15 19:50:45 +02:00
26e45d1ce4
phys: add support for dynamic rd/rdcmd/wr/wrcmd phases.
2020-09-14 18:57:20 +02:00
Florent Kermarrec