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1413 Commits

Author SHA1 Message Date
Florent Kermarrec 70c1491d1c ddr3_mr_gen: Display RZQ/x with --list (Useful for comparison with MIG's settings expressed in RZQ/x). 2022-02-24 14:44:02 +01:00
Florent Kermarrec e48471ea43 phy/s7ddrphy: Expose write_latency_calibration parameter and revert it to True by default. 2022-02-23 10:36:42 +01:00
Florent Kermarrec a0580c7ae7 frontend/axi: Add Write Buffer reservation mechanisms to know when we have enough data in the buffer to generate the command. 2022-02-17 17:21:02 +01:00
Florent Kermarrec 963233aefb litedram_gen: Add ECC support on ports and add example on kcu105. 2022-02-16 11:34:36 +01:00
Florent Kermarrec 68c082bf20 frontend/axi: Only switch between read/write at the end of a burst. 2022-02-15 18:05:47 +01:00
Florent Kermarrec 497bbc0394 frontend/axi: Improve similarities in aw/ar handling. 2022-02-15 17:43:38 +01:00
Florent Kermarrec 72ca120fa0 frontend/axi/LiteDRAMAXI2NativeW: Decouple axi.w from axi.aw and allow buffering in w_buffer without waiting for cmd to be accepted. 2022-02-15 17:34:09 +01:00
Florent Kermarrec 5f722a1513 bench/test: Avoid use of ident_version (should fix CI). 2022-02-15 17:33:31 +01:00
Florent Kermarrec e6758539d9 litedram_gen: Minor cosmetic cleanup. 2022-02-08 18:28:57 +01:00
Florent Kermarrec 24fad45764 frontend/dma/LiteDRAMDMAReader: Make sure to flush FIFO/Reservation counter when disabled. 2022-01-17 10:56:09 +01:00
Florent Kermarrec 62abf9ce0c litedram_gen: Add block_until_ready port parameter to control blocking behaviour. 
In some cases, blocking the port until controller is ready is not wanted (ex on No-CPU
config where a port is used for the memtest).
 2022-01-13 21:51:57 +01:00
Florent Kermarrec 2d47363f46 test/benchmark: Switch from soc_sdram (deprecated) to soc_core. 2022-01-07 18:37:13 +01:00
Florent Kermarrec e5e3b6c9a3 phy/s7ddrphy: Only do write latency calibration on Kintex7/Virtex7. 
This has been causing issues on Artix7 and is only required with write_leveling.
 2022-01-07 11:59:59 +01:00
Florent Kermarrec 1b0545cd60 Bump year. 2022-01-05 09:01:50 +01:00
enjoy-digital 6c0fe3ab6e
Merge pull request #290 from tongchen126/master 
add support for MT41K256M8 module
 2021-12-27 12:40:12 +01:00
tongchen126 15929e109d add support for MT41K256M8 module 2021-12-20 11:52:11 +08:00
Florent Kermarrec 17c19de8f8 frontend/dma: Move ack of write responses and other cosmetic cleanups. 2021-11-29 13:22:56 +01:00
enjoy-digital 925dbfd933
Merge pull request #286 from mkj/matt/orangecrab 
litedram_gen fixes for ECP5
 2021-11-29 08:36:11 +01:00
enjoy-digital 5b233742a4
Merge pull request #287 from cklarhorst/master 
add LPDDR module
 2021-11-29 08:34:21 +01:00
Florent Kermarrec 2113ecfba8 phy/usddrphy: Add missing iteration on pads.clk when multiple ranks. 2021-11-29 08:30:59 +01:00
Florent Kermarrec 81d318aa46 frontend/dma/LiteDRAMDMAWriter: Set b.ready to 1 on AXI port. 
Avoid having to do it externally.
 2021-11-26 11:51:49 +01:00
Christian Klarhorst 8226dca898 add LPDDR module 2021-11-25 14:18:05 +01:00
Matt Johnston 7560435d07 phy/ecp5ddrphy: Bring back dm_remapping 
This allows swapping UDM/LDM pins. Was removed in
af9abd6ec9
 phy/ecp5ddrphy: remove dm_remapping introduce for VexRiscv-SMP on OrangeCrab...

But is still useful for native port uses of litedram

Add dm_swap parameter to gen.py

Signed-off-by: Matt Johnston <matt@codeconstruct.com.au>
 2021-11-17 15:01:36 +08:00
enjoy-digital 78ff236ca7
Merge pull request #283 from antmicro/add-rdimms 
modules: add other RDIMM modules
 2021-11-06 08:30:41 +01:00
enjoy-digital 0eb59ebe88
Merge pull request #284 from hansfbaier/master 
W9825G6KH6 seems to use 8192 refresh cycles not 8000
 2021-11-06 08:30:09 +01:00
Hans Baier c3ec0ab079 W9825G6KH6 seems to use 8192 refresh cycles not 8000 2021-11-06 07:48:06 +07:00
Alessandro Comodi 021f243f6d modules: add other RDIMM modules 
Signed-off-by: Alessandro Comodi <acomodi@antmicro.com>
 2021-11-04 14:23:13 +01:00
Matt Johnston 06ca898c69 litedram_gen: Add ECLKBRIDGECS for ECP5 clock 
Signed-off-by: Matt Johnston <matt@codeconstruct.com.au>
 2021-11-03 14:06:26 +08:00
Matt Johnston 367231322d litedram_gen: Add pll_locked to ECP5 
Signed-off-by: Matt Johnston <matt@codeconstruct.com.au>
 2021-11-03 14:06:26 +08:00
Florent Kermarrec 3d1d711a43 modules/W9825G6KH6: Avoid specific comments/code. 
We have to keep things simple and avoid specific code preventing maintenance/evolutions.
 2021-11-01 23:03:34 +01:00
enjoy-digital bf7c06371f
Merge pull request #245 from hansfbaier/master 
add support for Winbond W9825G6KH-6 at 50MHz 1:2 rate
 2021-11-01 22:58:25 +01:00
enjoy-digital cea9d00d20
Merge pull request #270 from antmicro/jboc/lpddr5-rebase 
LPDDR5 support
 2021-11-01 22:18:38 +01:00
enjoy-digital 3b47170a0c
Merge pull request #273 from antmicro/rpc-dram-support 
Add RPC DRAM support
 2021-11-01 21:52:36 +01:00
Florent Kermarrec bf9b3609d9 frontend/fifo/LiteDRAMFIFO: Describe parameters. 2021-11-01 21:46:39 +01:00
Florent Kermarrec a8afbe8b08 test/test_refresh: Update. 2021-11-01 15:33:21 +01:00
Florent Kermarrec 5d7adcfa7c core/refresher: Add assert on clk_freq/tREFI ratio. 
Prevent generating a controller with tREFI too low to accept any transaction.
 2021-11-01 14:58:41 +01:00
Jean-François Nguyen 5aad6cd3d1 gen: use sys_clk_freq for SDRAMPHYModel timings, instead of 100MHz. 2021-11-01 14:28:19 +01:00
Alessandro Comodi c7721c4b93 ci: build and install latest verilator 
Signed-off-by: Alessandro Comodi <acomodi@antmicro.com>
 2021-10-26 12:40:02 +02:00
Alessandro Comodi f8ac00a8ab lpddr5: sim: add write leveling step as well 
Signed-off-by: Alessandro Comodi <acomodi@antmicro.com>
 2021-10-26 12:22:30 +02:00
Alessandro Comodi d7e2c82795 lpddr5: sim: fix non-syncronized pipe in simulation 
Signed-off-by: Alessandro Comodi <acomodi@antmicro.com>
 2021-10-26 12:22:30 +02:00
Alessandro Comodi 50ba27eb4c lpddr5: tests: add additional initial tCK delay for bitslip 
Signed-off-by: Alessandro Comodi <acomodi@antmicro.com>
 2021-10-26 12:22:30 +02:00
Alessandro Comodi ab130e170a lpddr5: add write leveling support 
Signed-off-by: Alessandro Comodi <acomodi@antmicro.com>
 2021-10-26 12:22:30 +02:00
Jędrzej Boczar ed6c7759b5 phy/lpddr5/sim: fix double reset with check_timings=False at high frequency 2021-10-26 12:22:30 +02:00
Jędrzej Boczar 43aef6255e phy/lpddr5: add Verilator tests 2021-10-26 12:22:30 +02:00
Jędrzej Boczar 2989963b9c phy: move regex pattern for parsing SimLogger logs to SimLogger class 2021-10-26 12:22:30 +02:00
Jędrzej Boczar aad7cce8c5 phy/lpddr5/simphy: use the same serialization scheme in S7 PHY to serve as reference 2021-10-26 12:22:30 +02:00
Jędrzej Boczar 6b2a1bc47c phy/lpddr5/s7phy: apply command serialization fixes 2021-10-26 12:22:30 +02:00
Alessandro Comodi abc77f367c lpddr5: wck sync: fix syncing and adjusted unit tests 
Signed-off-by: Alessandro Comodi <acomodi@antmicro.com>
 2021-10-26 12:22:30 +02:00
Alessandro Comodi c4273146c1 lpddr5: wck sync: adapt tests as now wck sync is required 
Signed-off-by: Alessandro Comodi <acomodi@antmicro.com>
 2021-10-26 12:22:30 +02:00
Alessandro Comodi c9954744df lpddr5: wck sync at every transaction 
Signed-off-by: Alessandro Comodi <acomodi@antmicro.com>
 2021-10-26 12:22:30 +02:00