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749 Commits 5 Branches 14 Tags 5.7 MiB
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749 Commits

Author SHA1 Message Date
Florent Kermarrec bd09471a03 phy/s7ddrphy: add 1:2 frequency ratio support (BC4 mode for now) 2018-07-13 17:31:39 +02:00
Florent Kermarrec dec5378422 core/bankmachine: add CAS to CAS support (tCCD) 2018-07-13 15:03:04 +02:00
Florent Kermarrec 5bc35759f6 modules: add retro-compat on MT41J256M16 2018-07-12 10:54:50 +02:00
Florent Kermarrec c4dad2402c modules: add description, add speedgrade support and improve tWTR/tFAW definition (in ck, ns or greater of ck/ns) 2018-07-10 12:13:59 +02:00
Florent Kermarrec 370b05ecf1 core/bankmachine: add Four Activate Window support (tFAW) 2018-07-09 17:27:58 +02:00
Florent Kermarrec d0ff536e0d phy/s7ddrphy: add specific bitslip reset 2018-07-06 19:27:18 +02:00
Florent Kermarrec 8ba7fcab23 core/bankmachine: simplify row change detection for auto precharge 2018-07-06 15:25:21 +02:00
Florent Kermarrec 3255a33b9e core/bankmachine: remove specific case for small cmd_buffer_depth 2018-07-06 14:49:12 +02:00
enjoy-digital d150e3b1ca
Merge pull request #12 from JohnSully/master 
Add auto-precharge support
 2018-07-06 14:41:08 +02:00
Florent Kermarrec 82b7199770 modules: fix tWTR for DDR3 modules (expressed in sys_clk not ns) 2018-07-06 14:32:13 +02:00
Florent Kermarrec f4b92b6142 phy/s7ddrphy: add nphases parameter to get functions 2018-07-04 21:55:43 +02:00
Florent Kermarrec d7d5d4a06f phy/s7ddrphy: add iodelay_clk_freq parameter 2018-07-02 13:43:15 +02:00
Florent Kermarrec f47ddb38e4 phy/s7ddrphy: add get_cl_cw function 2018-07-02 11:08:26 +02:00
Florent Kermarrec d9da7c54ee phy/s7ddrphy: compute phy settings automatically (based on tck) and add DDR3-1066/1333/1600 support. 2018-06-28 18:50:56 +02:00
Florent Kermarrec ba16ebfb22 phy: add common Series7 PHY (Artix7, Kintex7 & Virtex7) with or without ODELAY. Keep backward compatibility on imports. 2018-06-12 15:36:39 +02:00
Florent Kermarrec 2bd7707e67 modules: add MT18KSF1G72HZ_1G6 2018-06-12 09:54:38 +02:00
6b0d5ceeae Prevent spurious precharge all commands caused by leaving A10 asserted during precharge 2018-05-03 14:29:39 -04:00
d0fcfb172f Auto-precharge now only fires when it needs to 2018-05-03 03:34:21 -04:00
Florent Kermarrec c23814961d phy/kusddrphy: follow more Xilinx recommandations 2018-03-13 22:33:33 +01:00
Florent Kermarrec 45da365b7f phy/kusddrphy: add odelaye3 on all outputs (to have identical delays on all outputs before software dq/dqs delay configuration) 2018-03-09 20:46:19 +01:00
Florent Kermarrec f905fda8ff phy/kusddrphy: use IOBUFDSE3 on dqs to be able to apply ODT=RTT_40 constraint 2018-03-09 13:01:48 +01:00
Florent Kermarrec e6a99d9cbc phy/kusddrphy: revert dqs preamble/postamble since not working for continous transfer, will need a proper implementation 2018-03-08 13:15:28 +01:00
Florent Kermarrec 66d99a3e36 phy/kusddrphy: add dqs preamble/postamble instead of always toggling on oe_dqs 2018-03-08 10:44:48 +01:00
Florent Kermarrec da4651ff19 phy/kusddrphy: add comment 2018-03-08 08:33:31 +01:00
Florent Kermarrec 0d7a7a99e0 phy/kusddrphy: store dqs taps init value in csr at startup 2018-03-07 23:32:39 +01:00
Florent Kermarrec b885f582f3 phy/kusddrphy: operate delays in time mode (to be able to specify 500ps delay on dqs) and add workaround to allow software to get number of taps for 500ps at init. 2018-03-07 16:23:27 +01:00
Florent Kermarrec 459060ede3 phy/kusddrphy: add en_vtc control 2018-03-07 12:14:16 +01:00
Florent Kermarrec 48bc3cb15d README: add migen dependency 2018-03-01 10:43:08 +01:00
Florent Kermarrec 697f46a97f replace litex.gen imports with migen imports 2018-02-23 13:39:23 +01:00
Florent Kermarrec bd43fd605c bump to 0.2.dev 2018-02-23 13:39:06 +01:00
Florent Kermarrec 45a948d42a uniformize litex cores 2018-02-22 10:10:54 +01:00
Florent Kermarrec 58389534e6 modules: add MT47H64M16 2018-02-06 19:19:14 +01:00
Florent Kermarrec 57c63c1eab phy/a7ddrphy: make reset_n optional 2018-02-06 14:48:52 +01:00
Florent Kermarrec ec9ad2fc39 frontend/dma: add description of fifo_buffered parameter 2018-01-31 09:32:21 +01:00
Tim Ansell 13d41f67ab
Merge pull request #9 from felixheld/indentation-fixes 
Fix all remaining indentation issues in python code
 2018-01-13 13:38:02 +11:00
Felix Held 72b1b109b7 Fix all remaining indentation issues in python code 
I ran a script that shouldn't have missed any tab in the python source files.
 2018-01-13 13:22:08 +11:00
Florent Kermarrec a09b7a05b8 phy/kusddrphy: typo 2017-12-08 16:10:10 +01:00
Florent Kermarrec 010a6a2b91 phy/kusddrphy: use initial delay value on dqs instead of shifted sys4x clock 2017-12-08 15:52:52 +01:00
Florent Kermarrec 26d60fa781 doc: add simple architecture diagram 2017-11-13 18:49:35 +01:00
Florent Kermarrec eb6010d784 phy/kusddrphy: use locally inverted clk_b on iserdese3 2017-11-10 00:46:20 +01:00
Florent Kermarrec 38f1c268e9 phy/kusddrphy: reset bitslip on wdly_dq_rst instead of rdly_dq_rst 2017-11-08 21:52:56 +01:00
Florent Kermarrec f31f8a03ff modules: add MT46H32M32 2017-07-25 10:34:03 +02:00
Florent Kermarrec 47755e5637 phy/kusddrphy: fix typo on oserdese3/odatain (no functional impact) 2017-07-12 08:43:14 +02:00
Florent Kermarrec f251800fb6 phy/kusddrphy: use similar bitslip interface than kintex7 2017-07-10 15:50:47 +02:00
Florent Kermarrec 40a8504dd6 phy/kusddrphy: use specific sys4x_dqs clock since we can't ensure initial delay between dq/dqs using odelaye3 on ultrascale... 
tap delay can vary from 2.5 to 15ps across PVT
 2017-07-10 14:39:54 +02:00
Florent Kermarrec 5977a6fca0 phy/kusddrphy: remove comment on idelaye3 initial delay since fully covered by software 2017-07-10 13:59:24 +02:00
Florent Kermarrec 86b0cc0a56 frontend/bist: restrict lfsr to 32 bit allow bist with large ddram 
msbs data are then filled with zeros, but we should fix lfsr generation to avoid this
 2017-07-10 12:02:13 +02:00
Florent Kermarrec 33ca8d604e frontend/bist: use bytes for base and length parameters 2017-07-10 10:02:41 +02:00
Florent Kermarrec 7b31005bc4 phy/kusddrphy: fix input bit ordering, working :) 2017-07-08 18:46:53 +02:00
Florent Kermarrec 99fe71d622 phy/kusddrphy: revert delays control and add comments for initial delays values 2017-07-08 10:54:02 +02:00