Florent Kermarrec
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45a948d42a
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uniformize litex cores
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2018-02-22 10:10:54 +01:00 |
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Florent Kermarrec
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58389534e6
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modules: add MT47H64M16
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2018-02-06 19:19:14 +01:00 |
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Florent Kermarrec
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57c63c1eab
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phy/a7ddrphy: make reset_n optional
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2018-02-06 14:48:52 +01:00 |
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Florent Kermarrec
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ec9ad2fc39
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frontend/dma: add description of fifo_buffered parameter
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2018-01-31 09:32:21 +01:00 |
Tim Ansell
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13d41f67ab
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Merge pull request #9 from felixheld/indentation-fixes
Fix all remaining indentation issues in python code
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2018-01-13 13:38:02 +11:00 |
Felix Held
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72b1b109b7
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Fix all remaining indentation issues in python code
I ran a script that shouldn't have missed any tab in the python source files.
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2018-01-13 13:22:08 +11:00 |
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Florent Kermarrec
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a09b7a05b8
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phy/kusddrphy: typo
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2017-12-08 16:10:10 +01:00 |
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Florent Kermarrec
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010a6a2b91
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phy/kusddrphy: use initial delay value on dqs instead of shifted sys4x clock
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2017-12-08 15:52:52 +01:00 |
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Florent Kermarrec
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26d60fa781
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doc: add simple architecture diagram
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2017-11-13 18:49:35 +01:00 |
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Florent Kermarrec
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eb6010d784
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phy/kusddrphy: use locally inverted clk_b on iserdese3
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2017-11-10 00:46:20 +01:00 |
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Florent Kermarrec
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38f1c268e9
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phy/kusddrphy: reset bitslip on wdly_dq_rst instead of rdly_dq_rst
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2017-11-08 21:52:56 +01:00 |
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Florent Kermarrec
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f31f8a03ff
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modules: add MT46H32M32
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2017-07-25 10:34:03 +02:00 |
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Florent Kermarrec
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47755e5637
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phy/kusddrphy: fix typo on oserdese3/odatain (no functional impact)
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2017-07-12 08:43:14 +02:00 |
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Florent Kermarrec
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f251800fb6
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phy/kusddrphy: use similar bitslip interface than kintex7
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2017-07-10 15:50:47 +02:00 |
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Florent Kermarrec
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40a8504dd6
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phy/kusddrphy: use specific sys4x_dqs clock since we can't ensure initial delay between dq/dqs using odelaye3 on ultrascale...
tap delay can vary from 2.5 to 15ps across PVT
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2017-07-10 14:39:54 +02:00 |
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Florent Kermarrec
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5977a6fca0
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phy/kusddrphy: remove comment on idelaye3 initial delay since fully covered by software
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2017-07-10 13:59:24 +02:00 |
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Florent Kermarrec
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86b0cc0a56
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frontend/bist: restrict lfsr to 32 bit allow bist with large ddram
msbs data are then filled with zeros, but we should fix lfsr generation to avoid this
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2017-07-10 12:02:13 +02:00 |
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Florent Kermarrec
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33ca8d604e
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frontend/bist: use bytes for base and length parameters
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2017-07-10 10:02:41 +02:00 |
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Florent Kermarrec
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7b31005bc4
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phy/kusddrphy: fix input bit ordering, working :)
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2017-07-08 18:46:53 +02:00 |
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Florent Kermarrec
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99fe71d622
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phy/kusddrphy: revert delays control and add comments for initial delays values
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2017-07-08 10:54:02 +02:00 |
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Florent Kermarrec
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aad2f92b33
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phy/kusddrphy: IOBUF incorrect behaviour fixed by upgrading vivado to 2017.2...
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2017-07-08 10:13:58 +02:00 |
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Florent Kermarrec
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a72ba87f3e
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phy/kusddrphy: use fixed delays for initial board test, identify strange behaviour of IOBUF...
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2017-07-08 09:41:08 +02:00 |
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Florent Kermarrec
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7ea734381e
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phy/kusddrphy: phy has been simulated, remove from TODO
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2017-07-07 09:03:54 +02:00 |
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Florent Kermarrec
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b21a9d8e18
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phy/kusddrphy: add phy reset (just to be sure primitives are correctly reseted, will be removed if not needed)
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2017-07-07 09:02:58 +02:00 |
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Florent Kermarrec
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fa3535f7c0
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phy/kusddrphy: verify latencies with simulation
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2017-07-06 19:21:38 +02:00 |
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Florent Kermarrec
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abf028e0be
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global: reset_less optimizations
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2017-07-01 11:18:05 +02:00 |
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Florent Kermarrec
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67df00bcac
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frontend/bist: use new reset_less attribute where possible
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2017-06-29 11:20:08 +02:00 |
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Florent Kermarrec
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c8713bfb48
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litedram/frontend/bist: cleanup and add ticks counters to measure performance with hardware
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2017-06-29 10:41:34 +02:00 |
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Florent Kermarrec
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6091c6de60
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frontend: remove fifo, too complex to get working and too many corner cases (data stuck in pipeline, ...)
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2017-06-28 12:30:59 +02:00 |
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Florent Kermarrec
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369e9308b9
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frontend/fifo: simplify and only keep raw layout
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2017-06-27 17:24:32 +02:00 |
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Florent Kermarrec
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883e97101a
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common: add id to ports
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2017-06-27 15:06:12 +02:00 |
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Florent Kermarrec
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9ce2f67bb1
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frontend: add dram fifo (untested)
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2017-06-23 22:00:49 +02:00 |
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Florent Kermarrec
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bab0150c87
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README: consistency between projects
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2017-06-22 16:57:14 +02:00 |
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Florent Kermarrec
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25d5674f33
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test: remove test_bitslip (now in litex)
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2017-04-24 18:49:20 +02:00 |
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Florent Kermarrec
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3fe29ddacc
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phy: BitSlip now integrated in LiteX
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2017-04-19 09:58:27 +02:00 |
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Florent Kermarrec
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767b0144eb
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modules: add MT41J256M16
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2017-03-14 20:59:02 +01:00 |
|
Florent Kermarrec
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ddb05b92b6
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phy/kusddrphy: test implementation and fixes
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2017-03-14 09:20:06 +01:00 |
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Florent Kermarrec
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c04c288e66
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phy/kusddrphy: fix OSERDESE3/ISERDESE3 data ports
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2017-03-09 10:54:53 +01:00 |
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Florent Kermarrec
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98d9f1ffc0
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test/test_bitslip: simplify BitSlipModel
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2017-02-10 13:18:11 +01:00 |
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Florent Kermarrec
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cd83448f8e
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README: update copyright
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2017-02-10 13:08:09 +01:00 |
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Florent Kermarrec
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63434324e6
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phy/kusddrphy: add TODO
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2017-02-10 13:05:49 +01:00 |
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Florent Kermarrec
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ac43e0118e
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phy/x7ddrphy: ease understanding of read latency loop range
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2017-02-10 12:57:08 +01:00 |
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Florent Kermarrec
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478b8c1df3
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phy/kusddrphy: integrate BitSlip module (in fabric) and instanciate ISERDESE3
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2017-02-10 12:51:30 +01:00 |
|
Florent Kermarrec
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c94b1e7d0a
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phy: cleanup instances indentation
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2017-02-10 10:06:31 +01:00 |
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Florent Kermarrec
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062177502b
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phy: add bitslip module (we need to implement it in logic for Kintex Ultrascale since not provided by ISERDESE3)
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2017-02-10 08:59:13 +01:00 |
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Florent Kermarrec
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1430cb3d49
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phy: add initial Kintex Ultrascale PHY (incomplete)
Input deserializer still missing, need to implement bitslip in logic and use new fifo interface.
Others primitives should be fine.
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2017-02-09 13:25:45 +01:00 |
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Florent Kermarrec
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99550968e7
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test: move BISTDriver to common and use it in test_bist_async
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2017-01-17 15:18:10 +01:00 |
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Florent Kermarrec
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1bcab6303d
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setup.py: add test_suite
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2017-01-17 15:17:21 +01:00 |
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Florent Kermarrec
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d213a628f8
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test/test_bist: use generator to corrupt memory (allow testing base address on checker/generator)
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2017-01-17 14:35:34 +01:00 |
|
Florent Kermarrec
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40168db0b4
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test/test_bist: create BISTDriver to simplify test code
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2017-01-17 14:31:24 +01:00 |