2c5fc6621a
phy/gensdrphy: fix problems with half-rate phy, tested on minispartan6
2020-07-14 10:58:58 +02:00
7f55e2e2c5
phy/gensdrphy: add half-rate PHY
2020-07-13 17:03:01 +02:00
edd5e0ec78
phy/gensdrphy: padd clk to SDROutput/SDRInput/SDRTristate.
2020-07-08 07:00:11 +02:00
a8fa38e286
phy/ecp5ddrphy: cosmetic cleanups.
2020-06-30 09:25:44 +02:00
8c339b9945
litedram_gen: update ECP5 clocking.
2020-06-29 19:30:13 +02:00
f6cc1cdb08
litedram_gen: increase integrated_rom_size to 0x8000.
2020-06-29 19:28:11 +02:00
9044c10408
phy/ecp5ddrphy: use sys_rst instead of sys2x_rst as reset on primitives and do sys2x reset externally.
2020-06-29 16:09:14 +02:00
fa7d91a053
phy/ecp5: simplify/fix dqs_oe/dq_oe and revert BitSlip on dq_i_data.
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dq/dqs_oe was one cycle of and BitSlip on dq_i_data is required for correct initialization.
2020-06-29 16:06:56 +02:00
8c112c709c
Merge pull request #207 from ozbenh/sim-autoinit
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dfii: Really default to HW control
2020-06-10 10:36:05 +02:00
4580882c69
dfii: Really default to HW control
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Looks like there was a typo in commit
a595fe07f2
2020-06-10 16:06:46 +10:00
52d7dbe3a6
frontend/fifo: make sure FIFO is only used on LiteDRAMNativePort, expose writer/reader fifo depth, add separators and update copyrights.
2020-06-04 09:26:13 +02:00
c4c8803f4f
Merge pull request #204 from antmicro/jboc/spd-read
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Add DDR4 SPD EEPROM data parser
2020-06-04 08:54:59 +02:00
067e8a5eb3
Merge pull request #205 from antmicro/jboc/fifo
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frontend/fifo: increase FIFO level only after data has actually been written
2020-06-04 08:41:04 +02:00
e5179eb9ab
gen: fix LiteDRAMFIFO parameters
2020-06-03 17:39:45 +02:00
8fedc3fcd2
frontend/fifo: increase FIFO level after data has actually been written
2020-06-03 16:13:28 +02:00
992f80c68b
litedram_gen: add Ultrascale(+) support and KCU105 config file, remove cmd_delay on 7-series (not automatically calibrated).
2020-06-03 09:35:40 +02:00
361d250677
litedram_gen: avoid second S7PLL for iodelay clk, generate it from main S7PLL on CLKOUT0 (with fractional divide).
2020-06-03 09:04:00 +02:00
1b56dcf364
litedram_gen: add more memtype asserts, remove csr_alignment (now fixed to 32-bit).
2020-06-03 08:57:31 +02:00
a595fe07f2
dfii: simplify control using CSRFields.
2020-06-02 16:31:33 +02:00
899462c864
Merge pull request #202 from ozbenh/sim-autoinit
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Default to HW control for sim
2020-06-02 15:48:41 +02:00
863c45a114
test/spd_data: add missing files to tracking
2020-06-02 15:19:53 +02:00
cbd90877b0
modules/spd: select tFAW_min_ck depending on page size
2020-06-02 12:19:38 +02:00
a8f2c044c9
modules: add DDR4SPDData parser
2020-06-02 12:16:41 +02:00
d62fd24c81
Merge pull request #201 from antmicro/jboc/spd-read
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modules/spd: save SPD data in SDRAMModule
2020-06-01 21:16:58 +02:00
4233f86112
modules/spd: save SPD data in SDRAMModule to allow for runtime verification
2020-06-01 16:56:41 +02:00
f3f89ed8d1
Default to HW control for sim
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(needs corresponding sdram.c fix in litex)
Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
2020-06-01 23:44:59 +10:00
f23cb8056d
litedram_gen: revert builder.build(..., regular_comb=False).
2020-05-27 19:56:00 +02:00
d1db115d6c
litedram_gen: review/simplify #197 .
2020-05-27 19:42:40 +02:00
a8e281f7c5
Merge pull request #197 from ozbenh/standalone-sim
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Allow generation of a standalone sim model
2020-05-27 19:16:00 +02:00
83b9a1d798
Merge pull request #199 from antmicro/jboc/spd-read
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modules: add function for parsing SPD EEPROM dumps from BIOS firmware
2020-05-27 14:57:16 +02:00
d0f0c94652
phy/model: Don't generate empty mem_*.init files
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When using the SDRAM PHY model without specified init data, the
generator still generates a bunch of $readmemh for each bank
reading mem.init, mem_1.init etc... all of which are 0-sized files.
This is cumbersome especially when using a standalone model in
an external project.
This is fixed by having the default bank_init be set to a list
of "None" rather than a list of empty lists.
Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
2020-05-22 18:09:11 +10:00
b8d6da534f
gen: Allow generation of a standalone sim model
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If the --sim argument is passed, this generates a model using
the simulation platform and simulated PHY.
Note: The data_width is set to 16 for now, which matches the
Arty. I haven't yet figured out how to extract that info from
the data we have in the .yml
Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
2020-05-22 18:09:06 +10:00
cbe91bcd41
modules: add function for parsing SPD EEPROM dumps from BIOS firmware
2020-05-21 16:18:34 +02:00
639a31fdd2
test/test_timing: update test_txxd_controller.
2020-05-20 23:40:01 +02:00
3c1ab76bbc
litedram/common/tXXDController: only set reset to 1 when txxd is None.
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This avoids triggering a warning/error with Yosys.
2020-05-19 13:10:32 +02:00
e95af3f15b
Merge pull request #195 from enjoy-digital/bios-libs
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Init: Generate DFII defines in sdram_phy.h
2020-05-19 08:18:38 +02:00
fe48a9290c
test/reference: update.
2020-05-19 08:16:11 +02:00
c30910a9d2
init: generate DFII_CONTROL flags in sdram_phy.h instead of defining them in the BIOS.
2020-05-18 23:06:33 +02:00
5078b19bff
core/crossbar: remove retro-compat > 6 months old.
2020-05-18 18:51:56 +02:00
3b105d512b
modules: fix SDRAMRegisteredModule.
2020-05-15 21:39:00 +02:00
b2a5685396
Merge pull request #189 from daveshah1/ddr4_rdimm_init
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Add support for DDR4 RDIMMs
2020-05-15 21:34:43 +02:00
7ae4ad5b7d
modules: add SDR/DDR/DDR2/DDR3/DDR4 SDRAMModule (and Registered versions).
2020-05-15 21:27:43 +02:00
1f7d9eb0b9
litedram_gen: pass FPGA speedgrade to iodelay_pll.
2020-05-14 11:44:32 +02:00
22bd01c014
frontend/wishbone: simplify by reusing LiteDRAMNativePortConverter
2020-05-13 17:14:42 +02:00
f4871b9f13
litedram_gen: use default settings on wb_bus.
2020-05-13 14:50:06 +02:00
b0bde294c0
frontend/wishbone: fix wb2native missing wdata.ready when wb/port data widths differ
2020-05-13 10:14:00 +02:00
6fb8396d8e
litedram_gen: remove csr_base (no longer needed since CPUNone type will automatically set csr mapping to 0x00000000) and create a use bus with the same address_width as the main bus of the SoC.
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For some use cases, we will want to have the CPU + wb_ctrl interface.
2020-05-13 09:41:48 +02:00
79314f9549
frontend/wishbone: fix wdata.valid being high with old data, use cmd.last=1
2020-05-12 17:15:18 +02:00
000a352079
frontend/adaptation: delay sending write commands to prevent data loss during up-conversion
2020-05-12 17:15:18 +02:00
84fb7d338a
frontend/adaptation: refactor up-converter logic to use FSM for clarity
2020-05-12 17:14:58 +02:00
Jędrzej Boczar
Florent Kermarrec
Benjamin Herrenschmidt