cf83ac6422
test: improve SPD tests of Micron DDR3 SO-DIMM modules
2020-04-16 10:57:09 +02:00
45a03dff53
phy/init: add phytype to PhySettings and export more parameters to C header to simplify software.
...
Also:
- rename some paramters exported to software.
- simplify wlevel registers on A7DDRPHY (add then even if not used).
- move parameters computation in separate section.
2020-04-16 10:20:34 +02:00
854a614f99
modules: fix calculations of speedgrade from tck in SPD data
2020-04-16 10:12:23 +02:00
2df90040b7
init: improve ident.
2020-04-16 09:05:45 +02:00
eca7fc2ddc
phy/ecp5ddrphy: remove Bitslip from comment (no longer present).
2020-04-16 08:51:26 +02:00
f4f2948f61
phy/ecpddrphy: remove Bitslip (not used and redundant with dqs_read) and use BitSlip software control to move dqs_read.
2020-04-15 19:27:12 +02:00
c744204e1d
modules: fix nrows in MT8KTF51264
2020-04-15 16:20:55 +02:00
3980e062d5
modules: add option to load module parameters from SPD data
2020-04-15 16:20:55 +02:00
e2b4c2bfa1
phy/ecp5ddrphy: cosmetics.
2020-04-15 15:05:57 +02:00
f68f1ddfad
phy/ecp5ddrphy/control: cleanup/simplify and document (no functional changes).
2020-04-15 13:06:59 +02:00
fdf7c7613c
phy/control: cleanup/simplify (no functional changes).
2020-04-15 11:15:00 +02:00
a7676189b5
phy: improve flow control readability (add separators between Read/Write/Write DQS Postamble/Preamble parts).
2020-04-15 10:51:25 +02:00
de55a8e170
test/test_bandwidth: review, cleanup, fix typo.
2020-04-14 21:57:40 +02:00
907ef73971
test/test_wishbone: add comments/cleanup.
2020-04-14 21:48:44 +02:00
02fd39cf70
test/test_fifo: add comments.
2020-04-14 21:40:51 +02:00
14edb5b191
test/test_dma: add comments.
2020-04-14 19:51:31 +02:00
97e214b0dd
test/test_bist: add comments, fix a typo.
2020-04-14 19:44:58 +02:00
c55136c17a
test/test_bist: enable test_bist_csr_cdc (now passing with refactored CDC).
2020-04-14 18:14:05 +02:00
92e34d4d37
frontend/bist: simplify and fix CDC using AsyncFIFO.
2020-04-14 18:13:33 +02:00
378c4419c1
frontend/bist: rename run/ready to run_cascade_in/run_cascade_out.
2020-04-14 16:52:02 +02:00
829dee6a61
frontend/bist: remove run/ready CSR.
...
run/ready are only used when generator and checker are coupled together to do alternating write/read.
In this mode, run/ready are connected directly in the gateware and are not controlled by software.
2020-04-14 16:29:05 +02:00
b399ae2e36
test/benchmark: default value of run is 1, no need to drive it.
2020-04-14 13:00:39 +02:00
7c5e1e79da
frontend/bist: remove wrong comment and don't increment ticks when waiting.
2020-04-14 12:51:25 +02:00
4dbb5b1cbb
test/run_benchmarks: fix syntax.
2020-04-13 19:57:49 +02:00
966ebcbc41
test: cleanup/uniformize things between tests.
2020-04-13 19:38:29 +02:00
0efd619b46
test/test_adaption: review, add some comments.
2020-04-13 18:39:52 +02:00
38b78fc3e4
test/run_benchmarks: review, minor styles changes.
2020-04-13 18:27:16 +02:00
962dcd7d9a
phy/model: review/cleanup DFITimingsChecker.
2020-04-13 18:10:07 +02:00
64c2be5d63
README: switch to markdown.
2020-04-11 19:11:22 +02:00
835825b834
Merge pull request #179 from antmicro/jboc/docs
...
Add docstrings to litedram.core modules
2020-04-10 19:58:45 +02:00
969943e4c5
Merge pull request #178 from antmicro/jboc/unit-tests-crossbar
...
Add litedram.core.crossbar tests
2020-04-10 19:41:45 +02:00
06965b75a5
phy/gensdrphy: simplify using SDRTristate, change SDROutput/SDRInput to single-bit.
2020-04-10 14:45:59 +02:00
dbac83f411
core: add missing docstrings
2020-04-10 14:03:16 +02:00
8a0bcb3a2a
test: add core.crossbar tests
2020-04-10 12:46:10 +02:00
9d2064290b
litex.build: update from migen.genlib.io litex.build.io.
2020-04-10 09:20:05 +02:00
b9f4d9947c
phy/gensdrphy: use SDRInput, SDROutput to allow infered or instantiated IO regs.
2020-04-09 16:27:43 +02:00
e74a2e6a02
test: fix missing cases in bankmachine test
2020-04-08 10:31:34 +02:00
36d62d5301
Merge pull request #177 from antmicro/jboc/unit-tests-bankmachine
...
Add litedram.core.bankmachine tests
2020-04-08 09:55:20 +02:00
1f246cbb88
core/crossbar: remove dead code
2020-04-07 13:18:36 +02:00
492b9fa209
Merge pull request #175 from antmicro/jboc/unit-tests-bandwidth
...
Add core.bandwidth tests
2020-04-07 13:13:54 +02:00
cc7621df68
Merge pull request #173 from antmicro/jboc/unit-tests
...
Add litedram.core.multiplexer tests
2020-04-07 13:02:05 +02:00
e7cd6a7e2c
.travis.yml: udpate to keep it similar with others .travis.yml files.
2020-04-07 12:24:04 +02:00
7b8b68afcb
test: add core.bankmachine tests
2020-04-07 11:58:56 +02:00
0c3a610544
setup.py: simplify, switch to Python3.6+ (using python_requires), remove version.
...
- Deprecate Python 3.5, switch to Python 3.6+.
- Remove which was not used or updated. We'll see to get this back when working on releases.
2020-04-07 11:51:23 +02:00
a98f51e04e
dfii: use reset_less on datapath/configuration CSRStorages.
2020-04-06 13:17:47 +02:00
96b273c523
common/BitSlip: use reset_less on intermediate signal.
2020-04-06 11:59:34 +02:00
f0496b20ec
core/bandwidth: avoid missing a command
2020-04-03 13:26:17 +02:00
c03bed8ef6
test: add core.bandwidth.Bandwidth tests
2020-04-03 13:11:10 +02:00
a62e59bccf
test: skip _CommandChooser tests from Issue #174
2020-04-01 16:19:37 +02:00
00fcdf6da7
test: split core.multiplexer tests into separate files
2020-04-01 15:36:14 +02:00
Jędrzej Boczar
Florent Kermarrec
Jędrzej Boczar