Hardware
/
litedram
mirror of https://github.com/enjoy-digital/litedram.git
1
0
Fork 0
Code Issues Packages Projects Releases Wiki Activity
952 Commits 5 Branches 14 Tags 5.7 MiB
Commit Graph

952 Commits

Author SHA1 Message Date
Tim 'mithro' Ansell 8ff2f8779b bist: Adding "halt on error" functionality. 
Also include ability to see address of error and expected verse actual
data values.

Extend the test bench to test this functionality.
 2016-12-17 14:09:50 +01:00
Tim 'mithro' Ansell c0b8d1a714 bist: Adding some documentation. 
(Plus small formatting cleanup.)
 2016-12-17 14:09:50 +01:00
Tim 'mithro' Ansell da144f41d4 bist: Refactoring test bench. 
Move a bunch of common code into common.py
 2016-12-17 14:09:50 +01:00
Tim 'mithro' Ansell dc14a98bf4 bist: s/shoot/start/ 2016-12-17 14:09:50 +01:00
Tim 'mithro' Ansell 086b905e59 bist: Improve the basic test bench a little. 2016-12-17 14:09:50 +01:00
Tim 'mithro' Ansell 6ae11fa5c8 bist: Make reset write to activate like shoot. 2016-12-17 14:09:50 +01:00
Tim 'mithro' Ansell 85e4b65550 bist: Small formatting change. 2016-12-17 14:09:50 +01:00
Tim 'mithro' Ansell e901305e56 bist: Done only goes high after bist runs. 2016-12-17 14:09:50 +01:00
Florent Kermarrec f57dfad6a4 frontend: add flush signal on dram ports and fix a specific case in LiteDRAMReadPortUpConverter 2016-12-15 19:07:43 +01:00
Florent Kermarrec bd40268961 frontend/dma: add fifo_buffered parameter 2016-10-28 09:48:25 +02:00
Florent Kermarrec 6e3f5e4d98 frontend: add reverse parameter to converters 2016-06-21 17:29:12 +02:00
Florent Kermarrec 2ed7212701 frontend/crossbar: fix sign on adr_shift 2016-06-20 21:40:32 +02:00
Florent Kermarrec ad8ca86e13 frontend/adaptation: implement LiteDRAMReadPortUpConverter correctly 
still some corner cases to manage
 2016-06-15 23:57:16 +02:00
Florent Kermarrec 5823373243 frontend: introduce mode on ports: write, read or both 2016-06-15 17:51:46 +02:00
Florent Kermarrec b0382e8776 frontend/crossbar: add clock domain crossing and data width convertion to get_port 2016-06-13 14:41:57 +02:00
Florent Kermarrec ed997f1cfe core: fix refresh (bug was reducing controller throughput by 2) 2016-06-13 13:11:41 +02:00
Florent Kermarrec 870638fc50 frontend/adaptation: small optimization on LiteDRAMPortUpConverter (still to be refactored) 2016-06-12 16:53:44 +02:00
Florent Kermarrec edbebfa8a2 frontend/adaptation: add workaround on LiteDRAMPortUpConverter to increase throughput on reads (to be fixed since only working for our actual usecase) 2016-06-10 22:07:53 +02:00
Florent Kermarrec 66907f1468 frontend/adaptation: expose LiteDRAMPortDownConverter, LiteDRAMPortUpConverter 2016-06-10 19:13:12 +02:00
Florent Kermarrec e2b6bda7d0 test: add random and autocheck on downconverter_tb and upconverter_tb 2016-06-08 17:33:21 +02:00
Florent Kermarrec afd2e441eb frontend/adaptation: fix some comments 2016-06-08 17:32:08 +02:00
Florent Kermarrec 25c5a8aaf5 frontend/adaptation: adapt fifo depths 2016-06-02 22:35:27 +02:00
Florent Kermarrec 0faee6639d frontend/bist: add random parameter on generator/checker to ease debug 2016-06-02 18:35:45 +02:00
Florent Kermarrec a5ff573046 frontend/bist: rename generator/checker to core 2016-06-02 09:27:46 +02:00
Florent Kermarrec 41364dd0b1 frontend/bist: fix cd on LiteDRAMBISTChecker, bist_async_tb now working 2016-05-29 16:00:35 +02:00
Florent Kermarrec cb69561137 phy/model: add we_granularity parameter as simulator bug workaround (to be removed) 2016-05-28 13:02:40 +02:00
Florent Kermarrec 8ee2992e5b frontend/bist: simplify and use incrementing addressing 2016-05-26 12:04:41 +02:00
Florent Kermarrec 2445758eba +x on scripts 2016-05-26 11:10:03 +02:00
Florent Kermarrec b3a11fb669 frontend: move port adaptation modules to adaptation.py and do adaptation manually (and not in get_port) 2016-05-26 11:03:55 +02:00
Florent Kermarrec 3fe3a843e0 test: also test reads on downconverter/upconverter 2016-05-24 21:40:46 +02:00
Florent Kermarrec 32a6e25021 test: add upconverter_tb and some fixes 2016-05-24 21:14:49 +02:00
Florent Kermarrec de61cefb58 test: add downconverter_tb and some fixes 2016-05-24 20:48:26 +02:00
Florent Kermarrec 777d907da1 frontend/crossbar: fill LiteDRAMUpConverter (incomplete and to be tested) 2016-05-24 08:49:53 +02:00
Florent Kermarrec f70e28beac frontend/crossbar: fill LiteDRAMDownConverter (to be tested) 2016-05-24 08:34:14 +02:00
Florent Kermarrec b76f7e6e07 frontend/crossbar: add skeleton/descroption for port downconverters/upconverters 2016-05-24 06:56:58 +02:00
Tim 'mithro' Ansell 673a5d8317 Adding .gitignore file. 2016-05-23 19:59:56 +02:00
Florent Kermarrec 6f10314d43 frontend/bist: remove cd parameter (already available with dram_port.cd) 2016-05-23 17:37:30 +02:00
Florent Kermarrec b258c9a913 test: add bist_async_tb and some fixes 2016-05-23 17:20:42 +02:00
Florent Kermarrec cb42ea510d frontend/bist: LiteDRAMBISTChecker can now be asynchronous 2016-05-23 14:26:53 +02:00
Florent Kermarrec cb324ea47c frontend/bist: LiteDRAMBISTGenerator can now be asynchronous 2016-05-23 14:17:22 +02:00
Florent Kermarrec f36c65b66f test: move DRAMMemory model to common 2016-05-23 13:30:38 +02:00
Florent Kermarrec 94d526a78c test/bist_tb: adapt to new interface 2016-05-23 13:27:29 +02:00
Florent Kermarrec a016a820b5 common/LiteDRAMPort: add defaut cd value 2016-05-18 15:49:44 +02:00
Florent Kermarrec 8d066caea9 common: use cmd/wdata/rdata stream on LiteDRAMPort 2016-05-13 15:46:15 +02:00
Florent Kermarrec 30bacfeb1b frontend: add LiteDRAMAsyncAdapter for asynchronous ports (need more tests) 2016-05-13 15:27:12 +02:00
Florent Kermarrec 19a0bd59d2 frontend/dma: use stream.SyncFIFO 2016-05-13 13:35:59 +02:00
Florent Kermarrec 8b98dd3c8a frontend: simplify wdata/wdata_we on user side (implement the mux in the crossbar) 2016-05-12 15:34:39 +02:00
Florent Kermarrec 9d2c8bf1cf frontend: remove geom/timing parameters from LiteDRAMPort since this prevent providing async or arbitraty length port easily 2016-05-09 12:07:06 +02:00
Florent Kermarrec d7458a3c34 test: remove common 2016-05-04 01:16:29 +02:00
Florent Kermarrec 92c036e72b remove example_designs for now (examples are in LiteX) 2016-05-04 01:15:19 +02:00