Commit Graph

1189 Commits

Author SHA1 Message Date
Benjamin Herrenschmidt d0f0c94652 phy/model: Don't generate empty mem_*.init files
When using the SDRAM PHY model without specified init data, the
generator still generates a bunch of $readmemh for each bank
reading mem.init, mem_1.init etc... all of which are 0-sized files.

This is cumbersome especially when using a standalone model in
an external project.

This is fixed by having the default bank_init be set to a list
of "None" rather than a list of empty lists.

Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
2020-05-22 18:09:11 +10:00
Benjamin Herrenschmidt b8d6da534f gen: Allow generation of a standalone sim model
If the --sim argument is passed, this generates a model using
the simulation platform and simulated PHY.

Note: The data_width is set to 16 for now, which matches the
Arty. I haven't yet figured out how to extract that info from
the data we have in the .yml

Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
2020-05-22 18:09:06 +10:00
Jędrzej Boczar cbe91bcd41 modules: add function for parsing SPD EEPROM dumps from BIOS firmware 2020-05-21 16:18:34 +02:00
Florent Kermarrec 639a31fdd2 test/test_timing: update test_txxd_controller. 2020-05-20 23:40:01 +02:00
Florent Kermarrec 3c1ab76bbc litedram/common/tXXDController: only set reset to 1 when txxd is None.
This avoids triggering a warning/error with Yosys.
2020-05-19 13:10:32 +02:00
enjoy-digital e95af3f15b
Merge pull request #195 from enjoy-digital/bios-libs
Init: Generate DFII defines in sdram_phy.h
2020-05-19 08:18:38 +02:00
Florent Kermarrec fe48a9290c test/reference: update. 2020-05-19 08:16:11 +02:00
Florent Kermarrec c30910a9d2 init: generate DFII_CONTROL flags in sdram_phy.h instead of defining them in the BIOS. 2020-05-18 23:06:33 +02:00
Florent Kermarrec 5078b19bff core/crossbar: remove retro-compat > 6 months old. 2020-05-18 18:51:56 +02:00
Florent Kermarrec 3b105d512b modules: fix SDRAMRegisteredModule. 2020-05-15 21:39:00 +02:00
enjoy-digital b2a5685396
Merge pull request #189 from daveshah1/ddr4_rdimm_init
Add support for DDR4 RDIMMs
2020-05-15 21:34:43 +02:00
Florent Kermarrec 7ae4ad5b7d modules: add SDR/DDR/DDR2/DDR3/DDR4 SDRAMModule (and Registered versions). 2020-05-15 21:27:43 +02:00
Florent Kermarrec 1f7d9eb0b9 litedram_gen: pass FPGA speedgrade to iodelay_pll. 2020-05-14 11:44:32 +02:00
Jędrzej Boczar 22bd01c014 frontend/wishbone: simplify by reusing LiteDRAMNativePortConverter 2020-05-13 17:14:42 +02:00
Florent Kermarrec f4871b9f13 litedram_gen: use default settings on wb_bus. 2020-05-13 14:50:06 +02:00
Jędrzej Boczar b0bde294c0 frontend/wishbone: fix wb2native missing wdata.ready when wb/port data widths differ 2020-05-13 10:14:00 +02:00
Florent Kermarrec 6fb8396d8e litedram_gen: remove csr_base (no longer needed since CPUNone type will automatically set csr mapping to 0x00000000) and create a use bus with the same address_width as the main bus of the SoC.
For some use cases, we will want to have the CPU + wb_ctrl interface.
2020-05-13 09:41:48 +02:00
Jędrzej Boczar 79314f9549 frontend/wishbone: fix wdata.valid being high with old data, use cmd.last=1 2020-05-12 17:15:18 +02:00
Jędrzej Boczar 000a352079 frontend/adaptation: delay sending write commands to prevent data loss during up-conversion 2020-05-12 17:15:18 +02:00
Jędrzej Boczar 84fb7d338a frontend/adaptation: refactor up-converter logic to use FSM for clarity 2020-05-12 17:14:58 +02:00
Florent Kermarrec 94c215e852 litedram_gen: review/simplify #193, always add ddrctrl. 2020-05-12 16:21:04 +02:00
enjoy-digital f036ec2c26
Merge pull request #193 from ozbenh/standalone-cores
Improve standalone cores
2020-05-12 14:56:40 +02:00
Benjamin Herrenschmidt 04717b478b gen: Rename standalone core wishbone
Name it wb_ctrl rather than just wb, which makes the resulting
core signal names a bit more descriptive. IE. The DRAM control
bus (by opposition to the use/data buss(es).

Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
2020-05-12 21:59:01 +10:00
Benjamin Herrenschmidt b0838f70e3 gen: Add option to specify CSR alignment
On some standalone core implementations, such with Microwatt,
the main system bus is 64-bit, but the wishbone to access the
CSRs is 32-bit.

To avoid extra logic & muxes and just wire these together, it's
useful to be able to specify a larger alignemnt (64-bit) for the
CSRs so that the generated csr.h contains the right offsets.

Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
2020-05-12 21:58:13 +10:00
Benjamin Herrenschmidt d5a03b3d89 gen: Add option to generate DDRCTL on standalone cores
Microwatt will want that as it uses init_done to select whether
to run the SDRAM init code or the user code at reset.

Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
2020-05-12 21:56:33 +10:00
Benjamin Herrenschmidt efad6b3ca5 gen: Add option to specify CSR base for standalone cores
Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
2020-05-12 21:55:05 +10:00
Benjamin Herrenschmidt c91cbb597d gen: Remove obsolete bus_expose config option
Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
2020-05-12 21:54:47 +10:00
Florent Kermarrec 4e539ad76e litedram_gen: switch to SoCCore. 2020-05-12 09:21:36 +02:00
Florent Kermarrec ac33d29727 litedram_gen: simplify and expose bus when CPU is set to None. 2020-05-12 09:07:59 +02:00
Florent Kermarrec fe478382e1 litedram_gen: expose a Bus Slave port instead of a CSR port.
The logic overhead is minimal and it makes things easier with more flexibility:
- since the main Bus is arbitrated, CPU and Bus Slave can coexist.
- integration is easier in LiteX.
- bridging to APB/AXI is easier.
2020-05-11 22:47:09 +02:00
Jędrzej Boczar efe9a44c93 frontend/adaptation: clean up LiteDRAMNativePortUpConverter code 2020-05-11 16:47:43 +02:00
Jędrzej Boczar 2f35e9714d frontend/adaptation: fix error when read follows write to the same address 2020-05-11 16:11:40 +02:00
Jędrzej Boczar 1587ee3611 frontend/adaptation: use port.cmd.last instead of port.flush in up-converter 2020-05-11 15:28:32 +02:00
Jędrzej Boczar 35fa91c055 test/crossbar: up-conversion with mode="both" should be working now 2020-05-11 14:56:39 +02:00
Jędrzej Boczar 9b90a56e07 frontend/adaptation: combine read/write port up-converters and extend tests 2020-05-11 14:56:39 +02:00
Jędrzej Boczar 762cd6d0f1 test/adaptation: add port converter tests with mode="both" 2020-05-11 14:56:39 +02:00
Jędrzej Boczar 7a0f7a7ead test/common: fix error in test data 2020-05-11 14:56:39 +02:00
Jędrzej Boczar 1cc9656a2d test/crossbar: improve NativePortDriver to use separate generatos on data paths 2020-05-11 14:25:06 +02:00
Jędrzej Boczar 025e280804 test/crossbar: fix test that was not being run 2020-05-11 14:25:06 +02:00
Florent Kermarrec 52b49fb80e test/reference: update. 2020-05-09 18:02:42 +02:00
Florent Kermarrec 52ca3936fe modules: add MT41J512M16/MT41K512M16. 2020-05-09 16:37:24 +02:00
Florent Kermarrec 589957f115 phy: extend Bitslip capability to 2 sys_clk cycles. 2020-05-08 13:12:17 +02:00
Florent Kermarrec 5c0231d929 common/BitSlip: add cycles parameter to extend bitstlip to multiple system clock cycles. 2020-05-08 13:09:54 +02:00
Benjamin Herrenschmidt ed0810a1af gen: Optionally pass cpu_variant from YAML to SoC
This allows the right gcc options to be set when using for
example VexRiscv_Min.v

Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
2020-05-06 21:42:37 +02:00
David Shah 70054bacdb Add support for DDR4 RDIMMs
Signed-off-by: David Shah <dave@ds0.me>
2020-04-29 12:34:41 +01:00
enjoy-digital dfe6f90569
Merge pull request #188 from daveshah1/ddr4_dimm_x4
usddrphy: Support for x4 chip based DIMMs
2020-04-29 12:03:10 +02:00
enjoy-digital 9f136c0fce
Merge pull request #187 from daveshah1/add_MTA18ASF2G72PZ
modules: Add MTA18ASF2G72PZ DDR4 RDIMM
2020-04-29 12:01:52 +02:00
David Shah 5b4381bcd3 usddrphy: Support for x4 chip based DIMMs
Signed-off-by: David Shah <dave@ds0.me>
2020-04-29 10:47:31 +01:00
David Shah 97f0a3745b modules: Add MTA18ASF2G72PZ DDR4 RDIMM
Signed-off-by: David Shah <dave@ds0.me>
2020-04-29 10:40:19 +01:00
Florent Kermarrec 9a2d3f0eb9 common: add PHYPadsReducer to only use specific DRAM modules.
For example on KC705, to only use the 4 first modules (bytes):

from litedram.common import PHYPadsReducer
ddram_pads = platform.request("ddram")
ddram_pads = PHYPadsReducer(ddram_pads, modules=[0, 1, 2, 3])
self.submodules.ddrphy = s7ddrphy.K7DDRPHY(ddram_pads,
[...]

On Arty, to only use the second module (byte):
from litedram.common import PHYPadsReducer
ddram_pads = platform.request("ddram")
ddram_pads = PHYPadsReducer(ddram_pads, modules=[1])
self.submodules.ddrphy = s7ddrphy.A7DDRPHY(ddram_pads,
[...]
2020-04-29 10:34:34 +02:00