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1189 Commits

Author SHA1 Message Date
Florent Kermarrec 9d2064290b litex.build: update from migen.genlib.io litex.build.io. 2020-04-10 09:20:05 +02:00
Florent Kermarrec b9f4d9947c phy/gensdrphy: use SDRInput, SDROutput to allow infered or instantiated IO regs. 2020-04-09 16:27:43 +02:00
Jędrzej Boczar e74a2e6a02 test: fix missing cases in bankmachine test 2020-04-08 10:31:34 +02:00
enjoy-digital 36d62d5301
Merge pull request #177 from antmicro/jboc/unit-tests-bankmachine 
Add litedram.core.bankmachine tests
 2020-04-08 09:55:20 +02:00
Jędrzej Boczar 1f246cbb88 core/crossbar: remove dead code 2020-04-07 13:18:36 +02:00
enjoy-digital 492b9fa209
Merge pull request #175 from antmicro/jboc/unit-tests-bandwidth 
Add core.bandwidth tests
 2020-04-07 13:13:54 +02:00
enjoy-digital cc7621df68
Merge pull request #173 from antmicro/jboc/unit-tests 
Add litedram.core.multiplexer tests
 2020-04-07 13:02:05 +02:00
Florent Kermarrec e7cd6a7e2c .travis.yml: udpate to keep it similar with others .travis.yml files. 2020-04-07 12:24:04 +02:00
Jędrzej Boczar 7b8b68afcb test: add core.bankmachine tests 2020-04-07 11:58:56 +02:00
Florent Kermarrec 0c3a610544 setup.py: simplify, switch to Python3.6+ (using python_requires), remove version. 
- Deprecate Python 3.5, switch to Python 3.6+.
- Remove which was not used or updated. We'll see to get this back when working on releases.
 2020-04-07 11:51:23 +02:00
Florent Kermarrec a98f51e04e dfii: use reset_less on datapath/configuration CSRStorages. 2020-04-06 13:17:47 +02:00
Florent Kermarrec 96b273c523 common/BitSlip: use reset_less on intermediate signal. 2020-04-06 11:59:34 +02:00
Jędrzej Boczar f0496b20ec core/bandwidth: avoid missing a command 2020-04-03 13:26:17 +02:00
Jędrzej Boczar c03bed8ef6 test: add core.bandwidth.Bandwidth tests 2020-04-03 13:11:10 +02:00
Jędrzej Boczar a62e59bccf test: skip _CommandChooser tests from Issue #174 2020-04-01 16:19:37 +02:00
Jędrzej Boczar 00fcdf6da7 test: split core.multiplexer tests into separate files 2020-04-01 15:36:14 +02:00
Jędrzej Boczar f619bedda2 test: clean up the code of core.multiplexer 2020-04-01 15:03:30 +02:00
Jędrzej Boczar 1dd4227b34 test: add core.multiplexer.Multiplexer tests 2020-04-01 14:21:16 +02:00
Jędrzej Boczar ea9324601c test: add comments to core.multiplexer._Steerer tests 2020-03-30 16:00:20 +02:00
Jędrzej Boczar 26ce99320e test: add core.multiplexer._Steerer tests 2020-03-30 13:16:03 +02:00
Jędrzej Boczar f36b5a4fd2 test: add core.multiplexer._CommandChooser tests 2020-03-27 15:53:29 +01:00
Jędrzej Boczar a1b1abe329 test: use TestCase.subTest for more verbose error messages 2020-03-27 15:42:13 +01:00
enjoy-digital b06e946d09
Merge pull request #172 from antmicro/zcu104-sodimm 
modules: add MTA4ATF51264HZ DDR4 SO-DIMM
 2020-03-26 18:19:29 +01:00
Florent Kermarrec f6babda683 litedram_gen: fix LiteDRAMECP5DDRPHYCRG clkin freq (input_clk_freq and not sys_clk_freq). 2020-03-26 18:10:26 +01:00
Florent Kermarrec 7fab898afc litedram_gen: use replace_in_file from litex, add comment on phy selection. 2020-03-26 16:37:19 +01:00
Florent Kermarrec d4d9ab740e litedram_gen/lattice: use trellis toolchain and LFE5UM5G-45F device for now. 2020-03-26 16:32:58 +01:00
Piotr Binkowski 7238a9c0e2 modules: add MTA4ATF51264HZ DDR4 SO-DIMM 2020-03-26 16:18:16 +01:00
Florent Kermarrec 6951428af5 test/test_fifo: minor cleanup. 2020-03-26 12:23:25 +01:00
Florent Kermarrec 0ee9d7db5f test/test_ecc: review and cleanup. 2020-03-26 12:00:08 +01:00
Florent Kermarrec 265e79f2aa test/gen_config: review/cleanup. 2020-03-26 11:43:33 +01:00
Florent Kermarrec 2bb8f8fd22 test/gen_access_pattern: cleanup. 2020-03-26 11:03:43 +01:00
Florent Kermarrec 72d2bbf09d test/benchmarck: cleanup. 2020-03-26 10:46:11 +01:00
Florent Kermarrec 0cbdbf18ad test/run_benchmarks: avoid relative imports as done on others tests. 2020-03-26 10:17:02 +01:00
enjoy-digital 24c075ed3a
Merge pull request #171 from antmicro/jboc/unit-tests-fifo 
Add tests for litedram.frontend.fifo
 2020-03-26 09:40:17 +01:00
enjoy-digital 5919627a95
Merge pull request #170 from antmicro/jboc/unit-tests 
Add tests for litedram.frontend.adaptation
 2020-03-26 09:39:52 +01:00
Jędrzej Boczar 4fd6dc0ab6 test: split test_fifo_ctrl into 2 separate tests 2020-03-25 11:50:13 +01:00
Jędrzej Boczar 5d5bff3425 test: add frontend.fifo tests 2020-03-25 11:50:13 +01:00
Jędrzej Boczar 72b91a8fb7 test: add timeout_generator 2020-03-25 11:50:13 +01:00
Florent Kermarrec 043666672d phy/gensdrphy: sample rddata on sys_clk (assume clk generated to sdram is shifted), add cmd_latency parameter and simplify control logic. 2020-03-24 19:50:35 +01:00
Jędrzej Boczar c39a6bd059 test: use @unittest.skip instead of commenting out code 2020-03-24 14:35:28 +01:00
Jędrzej Boczar 0afacba2ca test: replace ConverterDUT.write_* with .write 2020-03-24 12:04:53 +01:00
Jędrzej Boczar 7f36717516 test: add LiteDRAMNativePortCDC tests 2020-03-24 11:55:24 +01:00
Jędrzej Boczar 1f8868e6e9 test: add frontend.adaptation tests for different conversion ratios 2020-03-24 11:12:11 +01:00
enjoy-digital ebdbcacc1d
Merge pull request #169 from antmicro/jboc/unit-tests 
Add LiteDRAMWishbone2Native tests
 2020-03-21 19:12:45 +01:00
Florent Kermarrec d96dd94d55 phy/s7ddrphy: add ISERDESE2 MEMORY mode support that uses DQS to sample the DQ datas. 
This also reduces read latency by 1 sys_clk cycle.
 2020-03-20 18:54:23 +01:00
Jędrzej Boczar f19d92b67f test: add wishbone tests with data width mismatch 2020-03-20 14:48:50 +01:00
Jędrzej Boczar 7996ee5143 test: add missing write-enable handling 2020-03-20 14:48:50 +01:00
Jędrzej Boczar 3c0fdf0710 test: handle 'we' in DRAMMemory, add memory debug messages 2020-03-20 14:48:39 +01:00
Jędrzej Boczar e8558f6f9f test: fix bits formatting 2020-03-20 13:18:24 +01:00
Jędrzej Boczar 7593b2d9b9 test: add basic wishbone test 2020-03-20 09:30:33 +01:00