e56f74e08b
test/reference: update.
2020-09-07 19:37:03 +02:00
ac825e5112
add SPDX License identifier to header and specify file is part of LiteDRAM.
2020-08-23 15:52:08 +02:00
198bcbab67
test/reference: update.
2020-08-07 23:14:09 +02:00
16fd46bf35
frontend: rename adaptation to adapter.
2020-08-05 11:10:42 +02:00
02e67ec7c5
Merge pull request #192 from antmicro/jboc/port-adaptation
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Implement LiteDRAMNativePortUpConverter with mode="both"
2020-07-28 19:02:33 +02:00
c4c8803f4f
Merge pull request #204 from antmicro/jboc/spd-read
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Add DDR4 SPD EEPROM data parser
2020-06-04 08:54:59 +02:00
8fedc3fcd2
frontend/fifo: increase FIFO level after data has actually been written
2020-06-03 16:13:28 +02:00
863c45a114
test/spd_data: add missing files to tracking
2020-06-02 15:19:53 +02:00
a8f2c044c9
modules: add DDR4SPDData parser
2020-06-02 12:16:41 +02:00
d62fd24c81
Merge pull request #201 from antmicro/jboc/spd-read
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modules/spd: save SPD data in SDRAMModule
2020-06-01 21:16:58 +02:00
4233f86112
modules/spd: save SPD data in SDRAMModule to allow for runtime verification
2020-06-01 16:56:41 +02:00
639a31fdd2
test/test_timing: update test_txxd_controller.
2020-05-20 23:40:01 +02:00
fe48a9290c
test/reference: update.
2020-05-19 08:16:11 +02:00
22bd01c014
frontend/wishbone: simplify by reusing LiteDRAMNativePortConverter
2020-05-13 17:14:42 +02:00
efe9a44c93
frontend/adaptation: clean up LiteDRAMNativePortUpConverter code
2020-05-11 16:47:43 +02:00
2f35e9714d
frontend/adaptation: fix error when read follows write to the same address
2020-05-11 16:11:40 +02:00
1587ee3611
frontend/adaptation: use port.cmd.last instead of port.flush in up-converter
2020-05-11 15:28:32 +02:00
35fa91c055
test/crossbar: up-conversion with mode="both" should be working now
2020-05-11 14:56:39 +02:00
9b90a56e07
frontend/adaptation: combine read/write port up-converters and extend tests
2020-05-11 14:56:39 +02:00
762cd6d0f1
test/adaptation: add port converter tests with mode="both"
2020-05-11 14:56:39 +02:00
7a0f7a7ead
test/common: fix error in test data
2020-05-11 14:56:39 +02:00
1cc9656a2d
test/crossbar: improve NativePortDriver to use separate generatos on data paths
2020-05-11 14:25:06 +02:00
025e280804
test/crossbar: fix test that was not being run
2020-05-11 14:25:06 +02:00
52b49fb80e
test/reference: update.
2020-05-09 18:02:42 +02:00
20a849c652
test/reference: update ddr4_init.h
2020-04-28 11:57:11 +02:00
cec3a994e8
Merge pull request #181 from antmicro/jboc/eeprom-timings
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Add option to load module data from DDR3 SPD EEPROM
2020-04-25 08:25:35 +02:00
312bce2bf1
modules: pass rate automatically when creating module from SPD data
2020-04-17 14:14:02 +02:00
07bbd79eaf
modules: update existsing SO-DIMM timings based on SPD data
2020-04-17 11:57:55 +02:00
d061e60611
test/reference: update.
2020-04-16 11:38:43 +02:00
cf83ac6422
test: improve SPD tests of Micron DDR3 SO-DIMM modules
2020-04-16 10:57:09 +02:00
854a614f99
modules: fix calculations of speedgrade from tck in SPD data
2020-04-16 10:12:23 +02:00
3980e062d5
modules: add option to load module parameters from SPD data
2020-04-15 16:20:55 +02:00
de55a8e170
test/test_bandwidth: review, cleanup, fix typo.
2020-04-14 21:57:40 +02:00
907ef73971
test/test_wishbone: add comments/cleanup.
2020-04-14 21:48:44 +02:00
02fd39cf70
test/test_fifo: add comments.
2020-04-14 21:40:51 +02:00
14edb5b191
test/test_dma: add comments.
2020-04-14 19:51:31 +02:00
97e214b0dd
test/test_bist: add comments, fix a typo.
2020-04-14 19:44:58 +02:00
c55136c17a
test/test_bist: enable test_bist_csr_cdc (now passing with refactored CDC).
2020-04-14 18:14:05 +02:00
378c4419c1
frontend/bist: rename run/ready to run_cascade_in/run_cascade_out.
2020-04-14 16:52:02 +02:00
829dee6a61
frontend/bist: remove run/ready CSR.
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run/ready are only used when generator and checker are coupled together to do alternating write/read.
In this mode, run/ready are connected directly in the gateware and are not controlled by software.
2020-04-14 16:29:05 +02:00
b399ae2e36
test/benchmark: default value of run is 1, no need to drive it.
2020-04-14 13:00:39 +02:00
4dbb5b1cbb
test/run_benchmarks: fix syntax.
2020-04-13 19:57:49 +02:00
966ebcbc41
test: cleanup/uniformize things between tests.
2020-04-13 19:38:29 +02:00
0efd619b46
test/test_adaption: review, add some comments.
2020-04-13 18:39:52 +02:00
38b78fc3e4
test/run_benchmarks: review, minor styles changes.
2020-04-13 18:27:16 +02:00
8a0bcb3a2a
test: add core.crossbar tests
2020-04-10 12:46:10 +02:00
e74a2e6a02
test: fix missing cases in bankmachine test
2020-04-08 10:31:34 +02:00
36d62d5301
Merge pull request #177 from antmicro/jboc/unit-tests-bankmachine
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Add litedram.core.bankmachine tests
2020-04-08 09:55:20 +02:00
7b8b68afcb
test: add core.bankmachine tests
2020-04-07 11:58:56 +02:00
c03bed8ef6
test: add core.bandwidth.Bandwidth tests
2020-04-03 13:11:10 +02:00
a62e59bccf
test: skip _CommandChooser tests from Issue #174
2020-04-01 16:19:37 +02:00
00fcdf6da7
test: split core.multiplexer tests into separate files
2020-04-01 15:36:14 +02:00
f619bedda2
test: clean up the code of core.multiplexer
2020-04-01 15:03:30 +02:00
1dd4227b34
test: add core.multiplexer.Multiplexer tests
2020-04-01 14:21:16 +02:00
ea9324601c
test: add comments to core.multiplexer._Steerer tests
2020-03-30 16:00:20 +02:00
26ce99320e
test: add core.multiplexer._Steerer tests
2020-03-30 13:16:03 +02:00
f36b5a4fd2
test: add core.multiplexer._CommandChooser tests
2020-03-27 15:53:29 +01:00
a1b1abe329
test: use TestCase.subTest for more verbose error messages
2020-03-27 15:42:13 +01:00
6951428af5
test/test_fifo: minor cleanup.
2020-03-26 12:23:25 +01:00
0ee9d7db5f
test/test_ecc: review and cleanup.
2020-03-26 12:00:08 +01:00
265e79f2aa
test/gen_config: review/cleanup.
2020-03-26 11:43:33 +01:00
2bb8f8fd22
test/gen_access_pattern: cleanup.
2020-03-26 11:03:43 +01:00
72d2bbf09d
test/benchmarck: cleanup.
2020-03-26 10:46:11 +01:00
0cbdbf18ad
test/run_benchmarks: avoid relative imports as done on others tests.
2020-03-26 10:17:02 +01:00
24c075ed3a
Merge pull request #171 from antmicro/jboc/unit-tests-fifo
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Add tests for litedram.frontend.fifo
2020-03-26 09:40:17 +01:00
4fd6dc0ab6
test: split test_fifo_ctrl into 2 separate tests
2020-03-25 11:50:13 +01:00
5d5bff3425
test: add frontend.fifo tests
2020-03-25 11:50:13 +01:00
72b91a8fb7
test: add timeout_generator
2020-03-25 11:50:13 +01:00
c39a6bd059
test: use @unittest.skip instead of commenting out code
2020-03-24 14:35:28 +01:00
0afacba2ca
test: replace ConverterDUT.write_* with .write
2020-03-24 12:04:53 +01:00
7f36717516
test: add LiteDRAMNativePortCDC tests
2020-03-24 11:55:24 +01:00
1f8868e6e9
test: add frontend.adaptation tests for different conversion ratios
2020-03-24 11:12:11 +01:00
f19d92b67f
test: add wishbone tests with data width mismatch
2020-03-20 14:48:50 +01:00
7996ee5143
test: add missing write-enable handling
2020-03-20 14:48:50 +01:00
3c0fdf0710
test: handle 'we' in DRAMMemory, add memory debug messages
2020-03-20 14:48:39 +01:00
e8558f6f9f
test: fix bits formatting
2020-03-20 13:18:24 +01:00
7593b2d9b9
test: add basic wishbone test
2020-03-20 09:30:33 +01:00
060d1807ad
Merge pull request #168 from antmicro/jboc/unit-tests-ecc
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Add unit tests for ECC
2020-03-19 18:24:43 +01:00
68d078cc78
test: add tests for LiteDRAMNativePortECCW/LiteDRAMNativePortECCR
2020-03-19 10:57:54 +01:00
03f93998b5
test: move DMA specific tests to test_dma.py
2020-03-19 09:13:28 +01:00
1b4647b2e1
test: add tests for LiteDRAMNativePortECC
2020-03-18 15:43:49 +01:00
36d5b42aa0
test: correct DMAReaderDriver/DMAWriterDriver logic
2020-03-17 15:37:50 +01:00
6ef623efae
test: cleanup test_bist.py code style
2020-03-17 14:23:08 +01:00
a883f88cca
test: add LiteDRAMDMAReader tests
2020-03-17 14:12:09 +01:00
d86ebd7e9d
test: add LiteDRAMDMAWriter tests
2020-03-17 12:39:10 +01:00
5618d2a54c
test: fix quotes
2020-03-17 09:45:28 +01:00
ef9b13d7e8
test: add tests for BIST modules with clock domain crossing
2020-03-16 16:38:58 +01:00
a00c8b7940
test: unify BIST tests, factor out repetitive code
2020-03-16 09:23:45 +01:00
13aeb3fd65
test: add _LiteDRAMBISTChecker/_LiteDRAMPatternChecker tests
2020-03-16 09:11:37 +01:00
ba83e5645c
test: add some more verbose _LiteDRAMBISTGenerator tests
2020-03-16 09:11:37 +01:00
239859d95b
test: add tests for _LiteDRAMPatternGenerator
2020-03-16 09:11:37 +01:00
ac06382b5a
test: split GenCheckDriver run into configure/run
2020-03-16 09:11:37 +01:00
c8423a08a3
test: exit with failure when no benchmarks succeeded
2020-03-12 14:16:21 +01:00
92daf53ea2
test: fix with_uart parameter (see litex/b29f443f)
2020-03-12 14:16:21 +01:00
b89ecdf919
test: add _LiteDRAMBISTGenerator tests
2020-03-11 15:38:13 +01:00
2ce64bd5fb
Fix copyrights
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Signed-off-by: Karol Gugala <kgugala@antmicro.com>
Signed-off-by: Mateusz Holenko <mholenko@antmicro.com>
2020-03-05 17:40:21 +01:00
8fee3c7edf
test/reference: update kc705 ddr3_init.h.
2020-03-05 11:35:12 +01:00
87578dd2e3
Merge pull request #153 from antmicro/jboc/issue-151
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test/benchmarks: add memtype to summary (#151 )
2020-02-20 14:00:27 +01:00
4f9d6e413f
Merge pull request #152 from antmicro/jboc/benchmark
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Benchmarks: add timeout parameter
2020-02-20 14:00:06 +01:00
19cbf7d967
test/benchmarks: add memtype to summary ( #151 )
2020-02-20 13:36:49 +01:00
Florent Kermarrec
Jędrzej Boczar
Jędrzej Boczar
Karol Gugala