97e214b0dd
test/test_bist: add comments, fix a typo.
2020-04-14 19:44:58 +02:00
c55136c17a
test/test_bist: enable test_bist_csr_cdc (now passing with refactored CDC).
2020-04-14 18:14:05 +02:00
92e34d4d37
frontend/bist: simplify and fix CDC using AsyncFIFO.
2020-04-14 18:13:33 +02:00
378c4419c1
frontend/bist: rename run/ready to run_cascade_in/run_cascade_out.
2020-04-14 16:52:02 +02:00
829dee6a61
frontend/bist: remove run/ready CSR.
...
run/ready are only used when generator and checker are coupled together to do alternating write/read.
In this mode, run/ready are connected directly in the gateware and are not controlled by software.
2020-04-14 16:29:05 +02:00
b399ae2e36
test/benchmark: default value of run is 1, no need to drive it.
2020-04-14 13:00:39 +02:00
7c5e1e79da
frontend/bist: remove wrong comment and don't increment ticks when waiting.
2020-04-14 12:51:25 +02:00
4dbb5b1cbb
test/run_benchmarks: fix syntax.
2020-04-13 19:57:49 +02:00
966ebcbc41
test: cleanup/uniformize things between tests.
2020-04-13 19:38:29 +02:00
0efd619b46
test/test_adaption: review, add some comments.
2020-04-13 18:39:52 +02:00
38b78fc3e4
test/run_benchmarks: review, minor styles changes.
2020-04-13 18:27:16 +02:00
962dcd7d9a
phy/model: review/cleanup DFITimingsChecker.
2020-04-13 18:10:07 +02:00
64c2be5d63
README: switch to markdown.
2020-04-11 19:11:22 +02:00
835825b834
Merge pull request #179 from antmicro/jboc/docs
...
Add docstrings to litedram.core modules
2020-04-10 19:58:45 +02:00
969943e4c5
Merge pull request #178 from antmicro/jboc/unit-tests-crossbar
...
Add litedram.core.crossbar tests
2020-04-10 19:41:45 +02:00
06965b75a5
phy/gensdrphy: simplify using SDRTristate, change SDROutput/SDRInput to single-bit.
2020-04-10 14:45:59 +02:00
dbac83f411
core: add missing docstrings
2020-04-10 14:03:16 +02:00
8a0bcb3a2a
test: add core.crossbar tests
2020-04-10 12:46:10 +02:00
9d2064290b
litex.build: update from migen.genlib.io litex.build.io.
2020-04-10 09:20:05 +02:00
b9f4d9947c
phy/gensdrphy: use SDRInput, SDROutput to allow infered or instantiated IO regs.
2020-04-09 16:27:43 +02:00
e74a2e6a02
test: fix missing cases in bankmachine test
2020-04-08 10:31:34 +02:00
36d62d5301
Merge pull request #177 from antmicro/jboc/unit-tests-bankmachine
...
Add litedram.core.bankmachine tests
2020-04-08 09:55:20 +02:00
1f246cbb88
core/crossbar: remove dead code
2020-04-07 13:18:36 +02:00
492b9fa209
Merge pull request #175 from antmicro/jboc/unit-tests-bandwidth
...
Add core.bandwidth tests
2020-04-07 13:13:54 +02:00
cc7621df68
Merge pull request #173 from antmicro/jboc/unit-tests
...
Add litedram.core.multiplexer tests
2020-04-07 13:02:05 +02:00
e7cd6a7e2c
.travis.yml: udpate to keep it similar with others .travis.yml files.
2020-04-07 12:24:04 +02:00
7b8b68afcb
test: add core.bankmachine tests
2020-04-07 11:58:56 +02:00
0c3a610544
setup.py: simplify, switch to Python3.6+ (using python_requires), remove version.
...
- Deprecate Python 3.5, switch to Python 3.6+.
- Remove which was not used or updated. We'll see to get this back when working on releases.
2020-04-07 11:51:23 +02:00
a98f51e04e
dfii: use reset_less on datapath/configuration CSRStorages.
2020-04-06 13:17:47 +02:00
96b273c523
common/BitSlip: use reset_less on intermediate signal.
2020-04-06 11:59:34 +02:00
f0496b20ec
core/bandwidth: avoid missing a command
2020-04-03 13:26:17 +02:00
c03bed8ef6
test: add core.bandwidth.Bandwidth tests
2020-04-03 13:11:10 +02:00
a62e59bccf
test: skip _CommandChooser tests from Issue #174
2020-04-01 16:19:37 +02:00
00fcdf6da7
test: split core.multiplexer tests into separate files
2020-04-01 15:36:14 +02:00
f619bedda2
test: clean up the code of core.multiplexer
2020-04-01 15:03:30 +02:00
1dd4227b34
test: add core.multiplexer.Multiplexer tests
2020-04-01 14:21:16 +02:00
ea9324601c
test: add comments to core.multiplexer._Steerer tests
2020-03-30 16:00:20 +02:00
26ce99320e
test: add core.multiplexer._Steerer tests
2020-03-30 13:16:03 +02:00
f36b5a4fd2
test: add core.multiplexer._CommandChooser tests
2020-03-27 15:53:29 +01:00
a1b1abe329
test: use TestCase.subTest for more verbose error messages
2020-03-27 15:42:13 +01:00
b06e946d09
Merge pull request #172 from antmicro/zcu104-sodimm
...
modules: add MTA4ATF51264HZ DDR4 SO-DIMM
2020-03-26 18:19:29 +01:00
f6babda683
litedram_gen: fix LiteDRAMECP5DDRPHYCRG clkin freq (input_clk_freq and not sys_clk_freq).
2020-03-26 18:10:26 +01:00
7fab898afc
litedram_gen: use replace_in_file from litex, add comment on phy selection.
2020-03-26 16:37:19 +01:00
d4d9ab740e
litedram_gen/lattice: use trellis toolchain and LFE5UM5G-45F device for now.
2020-03-26 16:32:58 +01:00
7238a9c0e2
modules: add MTA4ATF51264HZ DDR4 SO-DIMM
2020-03-26 16:18:16 +01:00
6951428af5
test/test_fifo: minor cleanup.
2020-03-26 12:23:25 +01:00
0ee9d7db5f
test/test_ecc: review and cleanup.
2020-03-26 12:00:08 +01:00
265e79f2aa
test/gen_config: review/cleanup.
2020-03-26 11:43:33 +01:00
2bb8f8fd22
test/gen_access_pattern: cleanup.
2020-03-26 11:03:43 +01:00
72d2bbf09d
test/benchmarck: cleanup.
2020-03-26 10:46:11 +01:00
Florent Kermarrec
Jędrzej Boczar
Jędrzej Boczar
Piotr Binkowski