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743 Commits 6 Branches 14 Tags 3.8 MiB
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743 Commits

Author SHA1 Message Date
Vamsi K Vytla 59e04608a8 Adds RGMII phy support for Xilinx Ultrascale Devices. Hardware tested on HTG-940 2019-09-04 15:11:20 -07:00
Florent Kermarrec ad187d35f2 add CONTRIBUTORS file and add copyright header to all files 2019-06-24 11:43:10 +02:00
Florent Kermarrec fd6d6c30ba mac: update imports 2019-06-24 11:23:13 +02:00
Florent Kermarrec a170acda0f change MAC location (next to phy/core/frontend), keep import retro-compatibility 2019-06-24 11:20:46 +02:00
Florent Kermarrec 789dadd8bf liteeth/software: remove libwip/libuip examples. 
libuip integration can be found in https://github.com/timvideos/HDMI2USB-litex-firmware/tree/master/firmware
 2019-06-17 21:17:52 +02:00
Florent Kermarrec 2424e62bf9 software: also include generated/mem.h 2019-05-20 09:00:25 +02:00
Florent Kermarrec e88fc507c8 software: remote ethmac_mem.h dependency (no longer exists in LiteX) 2019-05-19 19:29:04 +02:00
Florent Kermarrec b318300414 phy/ku_1000basex: keep tx/rx in reset until pll is fully reseted and locked 2019-04-11 21:51:09 +02:00
Florent Kermarrec e6c35cdec8 phy/ku_1000basex: incease pll_reset 2019-04-10 15:38:21 +02:00
Florent Kermarrec 816f592469 phy: add initial ECP5RGMII PHY 2019-02-25 14:45:19 +01:00
Florent Kermarrec b4c1cfe8c5 core/icmp: fix reply checksum when request checksum >= 0xf800 
need to add +1
 2019-02-24 23:30:46 +01:00
Florent Kermarrec 77fa4bfb1e phy: add Kintex7 1000BaseX PHY 2019-01-22 19:40:32 +01:00
Florent Kermarrec c2d8a467c9 phy: add Kintex Ultrascale PHY (copyright M-Labs Ltd) 2019-01-21 11:27:33 +01:00
Florent Kermarrec d7fdcbb1dc phy: add Spartan6 RGMII PHY 2018-12-18 08:58:16 +01:00
Florent Kermarrec 52c23015b0 frontend/etherbone: reduce default buffer_depth to 4 2018-10-30 11:21:06 +01:00
Florent Kermarrec 602ddec664 common: use reverse_bytes from litex.gen 2018-10-30 11:13:09 +01:00
Florent Kermarrec 40b99ecc05 test: use new RemoteClient import 2018-09-23 10:28:50 +02:00
Florent Kermarrec c370e9f71f phy/model: remove creation/deletion of ethernet tap (now handled by the simulator) 2018-09-20 22:49:37 +02:00
Florent Kermarrec 3d868449e9 core/mac/sram: fix code refactoring 2018-09-17 09:10:59 +02:00
Florent Kermarrec 5106bcdc0c core/mac/sram: simplify last_be code 2018-09-07 21:14:17 +02:00
Florent Kermarrec ce72e34f56 core/mac: pass endianness and use if for last_be gen/check 2018-09-07 10:35:27 +02:00
Florent Kermarrec 94af3d63d9 README: update and rename example_designs to examples 2018-08-31 08:26:37 +02:00
Florent Kermarrec 24b0d2b8c2 setup.py: fix exclude, add example_designs to exclude 2018-07-19 11:23:52 +02:00
Florent Kermarrec 4edba99b38 phy: remove s6rgmii (not working correctly). 
Alternative is to create a wrapper around the rgmii_if from Xilinx as it's done in opsis-soc
 2018-07-18 10:09:01 +02:00
Florent Kermarrec 6b872fd271 setup.py: exclude sim, test, doc directories 2018-07-18 09:40:20 +02:00
Florent Kermarrec 40d91f09c4 phy: use rx_dv instead of dv 2018-07-05 10:48:17 +02:00
Florent Kermarrec ba2fdc532d README: add 1000BaseX phy 2018-06-29 14:47:22 +02:00
Florent Kermarrec a2dbdd6d2b phy: add a7_1000basex phy (from misoc) 2018-06-29 14:26:19 +02:00
Florent Kermarrec 95849a0fed core/icmp: use buffered=True on buffer to allow tools to use block rams 2018-05-27 07:41:32 +02:00
Florent Kermarrec 33afda74f7 README: add migen dependency 2018-03-01 10:43:30 +01:00
Florent Kermarrec 79a6ba7709 replace litex.gen imports with migen imports 2018-02-23 13:40:09 +01:00
Florent Kermarrec c15f089eba bump to 0.2.dev 2018-02-23 13:39:53 +01:00
Florent Kermarrec c42aa09878 uniformize litex cores 2018-02-22 10:12:33 +01:00
enjoy-digital 4e08d6e9f9
Merge pull request #13 from felixheld/crc_pythonize 
pythonize CRC calculation
 2018-02-22 09:00:25 +01:00
Felix Held 9dcc7bc65e mac/crc.py: make crc calculation more pythonic 2018-02-21 23:20:03 +01:00
Felix Held 2ceaa74caf clarify the comments in mac/crc.py code 2018-02-21 23:05:32 +01:00
Tim Ansell 8fc7161036
Merge pull request #11 from felixheld/indentation-fixes 
Fix all remaining indentation issues in python code
 2018-01-13 13:36:32 +11:00
Felix Held 20af2bf201 Fix all remaining indentation issues in python code 
I ran a script that shouldn't have missed any tab in the python source files.
 2018-01-13 13:23:18 +11:00
Florent Kermarrec 2788294834 core/mac/sram: add csr for fifo level of sram reader (for the linux driver) 2017-12-31 07:12:55 +01:00
Florent Kermarrec c9ec30df2f core/mac: apply changes from misoc: remove gap_checker in rx, add preamble errors, fix preamble checker 2017-12-30 18:32:50 +01:00
Florent Kermarrec ccdb85bcb7 doc: add simple architecture diagram 2017-11-13 17:39:09 +01:00
Florent Kermarrec edb51944d5 Merge branch 'master' of https://github.com/enjoy-digital/liteeth 2017-11-06 19:02:42 +01:00
Florent Kermarrec a20ff49c90 example_designs/test: keep up to date with litescope 2017-11-06 19:01:51 +01:00
Florent Kermarrec 26c01a1627 core/mac/crc: fix crc_error generation 2017-11-01 23:23:02 +01:00
Florent Kermarrec eaf4acc3f5 core/mac: apply misoc changes (72faa2c) 2017-11-01 21:11:08 +01:00
Florent Kermarrec 937c240727 test: fix test_model 2017-09-25 13:12:30 +02:00
enjoy-digital 48fb4647bd Merge pull request #6 from enjoy-digital/port-1234 
Adding TCP port 1234 to Etherbone dissector.
 2017-09-01 15:23:22 +02:00
Tim Ansell 00e6ded2e9 Adding TCP port 1234 to Etherbone dissector. 
LiteEth designs seem to commonly use TCP port 1234.
 2017-09-01 23:16:09 +10:00
Florent Kermarrec c43fb269a7 frontend/etherbone: timing optimizations 2017-07-19 12:20:17 +02:00
Florent Kermarrec 042d3aee3e frontend/etherbone: fix cd="sys case 2017-07-15 22:10:48 +02:00